MOSFETS WITH IMPLANTED CHARGE COMPENSATION REGIONS
A semiconductor device includes a semiconductor layer having a first conductivity type, a well region in the semiconductor layer, the well region having a second conductivity type opposite the first conductivity type, a source region having the first conductivity type in the well region, and an implanted charge compensation region in the semiconductor layer beneath the well region. The source region is adjacent a channel region in the well region. A method of forming a semiconductor device includes forming a well region having a second conductivity type in a semiconductor layer having a first conductivity type opposite the second conductivity type, forming a source region having the first conductivity type in the well region, and implanting ions into the semiconductor layer to form a charge compensation region in the semiconductor layer beneath the well region. The source region is adjacent a channel region in the well region.
1 . A semiconductor device, comprising:
a semiconductor layer having a first conductivity type;
a well region in the semiconductor layer, the well region having a second conductivity type opposite the first conductivity type;
a source region in the well region, wherein the source region has the first conductivity type, wherein the source region is adjacent a channel region in the well region; and
an implanted charge compensation region in the semiconductor layer beneath the well region.
2 . The semiconductor device of claim 1 , wherein the charge compensation region increases a voltage blocking capability of the semiconductor device.
3 . The semiconductor device of claim 1 , further comprising a gate insulating layer on the semiconductor layer above the channel region, a gate contact on the gate insulating layer, and a first contact on the source region.
4 . The semiconductor device of claim 3 , further comprising a substrate having the first conductivity type, wherein the semiconductor layer is on the substrate, and a second contact on the substrate.
5 . The semiconductor device of claim 1 , wherein the charge compensation region comprises non-activated implanted dopant ions.
6 . The semiconductor device of claim 1 , wherein the semiconductor layer comprises silicon carbide, and wherein the charge compensation region comprises hydrogen, aluminum or nitrogen dopant ions.
7 . The semiconductor device of claim 1 , wherein the semiconductor layer comprises silicon carbide, and wherein the charge compensation region comprises inert ions.
8 . The semiconductor device of claim 7 , wherein the inert ions comprise He, Ne, and/or Ar ions.
9 . The semiconductor device of claim 1 , wherein the semiconductor layer comprises silicon carbide, and wherein the charge compensation region comprises dopant ions that form deep level traps in the semiconductor layer.
10 . The semiconductor device of claim 5 , wherein the dopant ions comprise carbon and/or iron.
11 . The semiconductor device of claim 1 , wherein the charge compensation region decreases an electric field strength in the semiconductor layer in an area around the charge compensation region during a voltage blocking operation of the device.
12 . The semiconductor device of claim 1 , further comprising a doped well contact region in the semiconductor layer adjacent the source region, wherein the well contact region has the second conductivity type and contacts the well region, wherein the charge compensation region is at least partially provided beneath the well contact region.
13 . The semiconductor device of claim 1 , further comprising a doped well contact region in the semiconductor layer adjacent the source region, wherein the well contact region has the second conductivity type and contacts the well region, wherein the charge compensation region is not provided directly beneath the well contact region.
14 . The semiconductor device of claim 1 , wherein the charge compensation region is spaced apart from the well region in a vertical direction.
15 . The semiconductor device of claim 1 , further comprising a vertical conduction region adjacent the well region, wherein the charge compensation region is formed beneath a lower corner of the well region near the vertical conduction region.
16 . The semiconductor device of claim 15 , wherein the charge compensation region extends past the lower corner of the well region and into the vertical conduction region.
17 . A method of forming a semiconductor device, comprising:
forming a well region in a semiconductor layer, wherein the semiconductor layer has a first conductivity type, and the well region has a second conductivity type opposite the first conductivity type;
forming a source region in the well region, wherein the source region has the first conductivity type, wherein the source region is adjacent a channel region in the well region; and
implanting ions into the semiconductor layer to form a charge compensation region in the semiconductor layer beneath the well region.
18 . The method of claim 17 , wherein the charge compensation region increases a voltage blocking capability of the semiconductor device.
19 . The method of claim 17 , wherein the semiconductor layer comprises silicon carbide, and wherein forming the charge compensation region comprises implanting aluminum or nitrogen dopant ions into the semiconductor layer.
20 . The method of claim 17 , wherein the semiconductor layer comprises silicon carbide, and wherein the charge compensation region comprises dopant ions that form deep level traps in the semiconductor layer.
21 . The method of claim 20 , wherein the dopant ions comprise carbon and/or iron.
22 . The method of claim 17 , wherein the semiconductor layer comprises silicon carbide, and wherein implanting ions comprises implanting inert ions.
23 . The method of claim 22 , wherein the inert ions comprise He, Ne, and/or Ar ions.
24 . The method of claim 17 , wherein the charge compensation region decreases an electric field strength in the semiconductor layer in an area around the charge compensation region during a voltage blocking operation of the device.
25 . The method of claim 17 , further comprising forming a doped well contact region in the semiconductor layer adjacent the source region, wherein the well contact region has the second conductivity type and contacts the well region, wherein the charge compensation region is at least partially formed beneath the well contact region.
26 . The method of claim 17 , further comprising forming a doped well contact region in the semiconductor layer adjacent the source region, wherein the well contact region has the second conductivity type and contacts the well region, wherein the charge compensation region is not provided directly beneath the well contact region.
27 . The method of claim 17 , wherein the charge compensation region is spaced apart from the well region in a vertical direction.
28 . The method of claim 17 , further comprising forming a vertical conduction region adjacent the well region, wherein the charge compensation region is formed beneath a lower corner of the well region near the vertical conduction region.
29 . The method of claim 28 , wherein the charge compensation region extends past the lower corner of the well region and into the vertical conduction region.
30 . The method of claim 17 , further comprising forming a gate insulating layer on the semiconductor layer above the channel region, a gate contact on the gate insulating layer, and a first contact on the source region.
31 . The method of claim 30 , further comprising providing a substrate having the first conductivity type, wherein the semiconductor layer is formed on the substrate, and
forming a second contact on the substrate.