IP Library Granted Patent US 12,620,530
Granted Patent B2
US 12,620,530 · App. 17/951,523 · Granted May 5, 2026

Device and process for implementing silicon carbide (SiC) surface mount devices

Inventors: Kok Meng Kam (Ipoh, MY); Eng Wah Woo (Ipoh, MY); Samantha Cheang (Ipoh, MY); Marvin Marbell (Cary, NC); Haedong Jang (San Jose, CA); Jeremy Fisher (Raleigh, NC); Basim Noori (Durham, NC)
Assignee: Wolfspeed, Inc.
H01G4/228H10D1/692H10W20/20H10W90/00H10W72/07336H10W72/921H10W72/952H10W90/734
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Quick Facts
Patent No.
US 12,620,530
App. No.
17/951,523
Granted
May 5, 2026
Kind
B2
Abstract

In some aspects, a device includes a substrate. A first metallization arranged on the substrate. A second metallization arranged on the substrate. A circuit arranged on the substrate and electrically connected to the first metallization and the second metallization. The first metallization and the second metallization being configured, structured, and arranged to make a solder connection to a device, where the substrate may include silicon carbide (SiC).

Claims (106)

1 . A silicon carbide (SiC) surface mount device (SMD) comprising:

a substrate comprising a first surface and a second surface opposite the first surface;

a first metallization arranged on the first surface and the second surface of the substrate;

a second metallization arranged on the first surface and the second surface of the substrate;

a circuit arranged on the substrate and electrically connected to the first metallization and the second metallization; and

the first metallization and the second metallization being configured, structured, and arranged to make a solder connection to a device,

wherein the substrate comprises silicon carbide (SiC).

2 . The silicon carbide (SiC) surface mount device (SMD) according to claim 1

wherein the circuit is on the first surface of the substrate;

wherein the first metallization comprises a first top-side metallization; and

wherein the second metallization comprises a second top-side metallization.

3 . The silicon carbide (SiC) surface mount device (SMD) according to claim 2

wherein the circuit is on the first surface of the substrate and the circuit is configured to electrically connect to the first top-side metallization and the second top-side metallization.

4 . The silicon carbide (SiC) surface mount device (SMD) according to claim 2

wherein the silicon carbide (SiC) surface mount device (SMD) is configured as a flip Chip device; and

wherein the first top-side metallization and the second top-side metallization are configured as SMD leads configured, structured, and arranged to make the solder connection to the device.

5 . The silicon carbide (SiC) surface mount device (SMD) according to claim 1

wherein the first metallization comprises a first bottom-side metallization and a first top-side metallization;

wherein the second metallization comprises a second bottom-side metallization and a second top-side metallization; and

wherein the substrate comprises at least one via connected to the first bottom-side metallization and the first top-side metallization and/or wherein the substrate comprises at least one via connected to the second bottom-side metallization and the second top-side metallization.

6 . The silicon carbide (SiC) surface mount device (SMD) according to claim 1

wherein the device comprises a device substrate;

wherein the device substrate comprises a printed circuit board (PCB), a printed wiring board (PWB), and/or a printed circuit board assembly (PCBA); and

wherein the first metallization and the second metallization being configured, structured, and arranged to make a solder connection to the device substrate.

7 . The silicon carbide (SiC) surface mount device (SMD) according to claim 1

wherein the substrate comprises at least one via connected to the first metallization and/or the second metallization; and

wherein the circuit comprises at least a capacitor, an inductor, a spiral inductor, a transmission line, a resistor, and/or combinations thereof.

8 . The silicon carbide (SiC) surface mount device (SMD) according to claim 1

wherein the substrate comprises at least one via connected to the first metallization and/or the second metallization; and

wherein the silicon carbide (SiC) surface mount device (SMD) comprises at least a Metal-Insulator-Metal (MIM) capacitor with a first metal and a second metal having a dielectric layer therebetween.

9 . A device implementing the silicon carbide (SiC) surface mount device (SMD) according to claim 1 , the device comprising:

a device substrate;

a first top metal on the device substrate;

a second top metal on the device substrate;

a first solder portion arranged on the first top metal; and

a second solder portion arranged on the second top metal,

wherein the device substrate comprises a printed circuit board (PCB), a printed wiring board (PWB), and/or a printed circuit board assembly (PCBA).

10 . The device implementing the silicon carbide (SiC) surface mount device (SMD) according to claim 9 further comprising:

a first solder mask; and

a second solder mask,

wherein the first solder mask is arranged on the first top metal of the device; and

wherein the second solder mask is arranged on the second top metal of the device.

11 . The device implementing the silicon carbide (SiC) surface mount device (SMD) according to claim 10 wherein the first solder mask and the second solder mask are configured to contain reflowed solder such that the silicon carbide (SiC) surface mount device (SMD) self-aligns to a more exact intended placement position on the device substrate of the device.

12 . The device implementing the silicon carbide (SiC) surface mount device (SMD) according to claim 10

wherein the first solder mask comprises a first portion, a second portion, and a third portion;

wherein the first portion of the first solder mask is configured to connect to the second portion of the first solder mask; and

wherein the second portion of the first solder mask is configured to connect to the third portion of the first solder mask.

13 . The device implementing the silicon carbide (SiC) surface mount device (SMD) according to claim 12 wherein the first portion of the first solder mask, the second portion of the first solder mask, and the third portion of the first solder mask are configured to form a U-shape on the first top metal.

14 . The device implementing the silicon carbide (SiC) surface mount device (SMD) according to claim 9 wherein the silicon carbide (SiC) surface mount device (SMD) is configured to be attached to the device substrate using the first solder portion and/or the second solder portion.

15 . The silicon carbide (SiC) surface mount device (SMD) according to claim 1 wherein the substrate comprises semi-insulating silicon carbide.

16 . A process of implementing a silicon carbide (SiC) surface mount device (SMD) comprising:

providing a substrate comprising a first surface and a second surface opposite the first surface;

arranging a first metallization on the first surface and the second surface of the substrate;

arranging a second metallization on the first surface and the second surface of the substrate;

arranging a circuit electrically connected to the first metallization and the second metallization; and

reflowing a solder to connect the first metallization and the second metallization to a device,

wherein the substrate comprises silicon carbide (SiC).

17 . The process of implementing a silicon carbide (SiC) surface mount device (SMD) according to claim 16

wherein the circuit is on the first surface of the substrate;

wherein the first metallization comprises a first top-side metallization; and

wherein the second metallization comprises a second top-side metallization.

18 . The process of implementing a silicon carbide (SiC) surface mount device (SMD) according to claim 17

wherein the silicon carbide (SiC) surface mount device (SMD) is configured as a flip Chip device; and

wherein the first top-side metallization and the second top-side metallization are configured, structured, and arranged to make a solder connection to the device.

19 . The process of implementing a silicon carbide (SiC) surface mount device (SMD) according to claim 17 further comprising electrically connecting the circuit to the first top-side metallization and the second top-side metallization.

20 . The process of implementing a silicon carbide (SiC) surface mount device (SMD) according to claim 16

wherein the device comprises a device substrate;

wherein the device substrate comprises a printed circuit board (PCB), a printed wiring board (PWB), and/or a printed circuit board assembly (PCBA); and

wherein the first metallization and the second metallization being configured, structured, and arranged to make a solder connection to the device substrate.

21 . The process of implementing a silicon carbide (SiC) surface mount device (SMD) according to claim 16

wherein the first metallization comprises a first bottom-side metallization and a first top-side metallization;

wherein the second metallization comprises a second bottom-side metallization and a second top-side metallization; and

wherein the substrate comprises at least one via connected to the first bottom-side metallization and the first top-side metallization and/or wherein the substrate comprises at least one via connected to the second bottom-side metallization and the second top-side metallization.

22 . The process of implementing a silicon carbide (SIC) surface mount device (SMD) according to claim 16

wherein the substrate comprises at least one via connected to the first metallization and/or the second metallization; and

wherein the circuit comprises at least a capacitor, an inductor, a spiral inductor, a transmission line, a resistor, and/or a combinations thereof.

23 . The process of implementing a silicon carbide (SiC) surface mount device (SMD) according to claim 16

wherein the substrate comprises at least one via connected to the first metallization and/or the second metallization; and

wherein the silicon carbide (SiC) surface mount device (SMD) comprises at least a Metal-Insulator-Metal (MIM) capacitor with a first metal and a second metal having a dielectric layer therebetween.

24 . A process of implementing a device implementing the silicon carbide (SiC) surface mount device (SMD) according to claim 16 , the process of implementing a device comprising:

providing a device substrate;

arranging a first top metal on the device substrate;

arranging a second top metal on the device substrate;

arranging a first solder portion arranged on the first top metal; and

arranging a second solder portion arranged on the second top metal,

wherein the device substrate comprises a printed circuit board (PCB), a printed wiring board (PWB), and/or a printed circuit board assembly (PCBA).

25 . The process of implementing a device implementing the silicon carbide (SiC) surface mount device (SMD) according to claim 24 further comprising:

arranging a first solder mask on the first top metal of the device; and

arranging a second solder mask on the second top metal of the device.

26 . The process of implementing a device implementing the silicon carbide (SiC) surface mount device (SMD) according to claim 25 wherein the first solder mask and the second solder mask are configured to contain reflowed solder such that the silicon carbide (SiC) surface mount device (SMD) self-aligns to a more exact intended placement position on the device substrate of the device.

27 . The process of implementing a device implementing the silicon carbide (SiC) surface mount device (SMD) according to claim 25

wherein the first solder mask comprises a first portion, a second portion, and a third portion;

wherein the first portion of the first solder mask is configured to connect to the second portion of the first solder mask; and

wherein the second portion of the first solder mask is configured to connect to the third portion of the first solder mask.

28 . The process of implementing a device implementing the silicon carbide (SiC) surface mount device (SMD) according to claim 27 wherein the first portion of the first solder mask, the second portion of the first solder mask, and the third portion of the first solder mask are configured to form a U-shape on the first top metal.

29 . The process of implementing a silicon carbide (SiC) surface mount device (SMD) according to claim 16 wherein the substrate comprises semi-insulating silicon carbide.

30 . The process of implementing a device implementing the silicon carbide (SiC) surface mount device (SMD) according to claim 24 wherein the silicon carbide (SiC) surface mount device (SMD) is configured to be attached to the device substrate using the first solder portion and/or the second solder portion.

31 . A device comprising:

a silicon carbide substrate comprising a first surface and a second surface opposite the first surface;

a first metallization on the first surface and the second surface of the silicon carbide substrate

a first via between the first surface and the second surface and electrically connecting the first metallization on the first surface and the second surface;

a second metallization on the first surface and the second surface of the silicon carbide substrate;

a second via between the first surface and the second surface and electrically connecting the second metallization on the first surface and the second surface

a circuit on the first surface of the silicon carbide substrate and electrically connected to the first metallization and the second metallization; and

a device substrate comprising a first solder connection with the first metallization and a second solder connection with the second metallization.

32 . The device according to claim 31 wherein the silicon carbide substrate comprises semi-insulating silicon carbide.

Assignments (8)
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Mar 26, 2026
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 075280/0919 →
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL AT REEL/FRAME NO. 64185/0755 Recorded Sep 30, 2025
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WOLFSPEED, INC.
Reel/Frame 072989/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0113 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0381 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0467 →
NOTICE OF GRANT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Sep 30, 2025
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 072992/0588 →
SECURITY INTEREST Recorded Jun 30, 2023
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
Reel/Frame 064185/0755 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2023
From: KAM, KOK MENG; WOO, ENG WAH; CHEANG, SAMANTHA; JANG, HAEDONG; MARBELL, MARVIN; FISHER, JEFEMY; NOORI, BASIM
To: WOLFSPEED, INC.
Reel/Frame 063314/0633 →
Continuity (1)
Related Publication 20240105390A1 · Mar 28, 2024
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