Vertical power transistor device
A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.
1. A transistor device comprising a gate, a source, and a drain, wherein the gate and the source are separated from the drain by at least a JFET region, a spreading layer including a graded doping profile, and a drift layer, wherein a doping concentration of the spreading layer varies more than a factor of about 10 2 cm −3 between the JFET region and the drift layer, a thickness of the JFET region is between 0.75 μm and 1.5 μm, a pair of junction implants is in the spreading layer such that the pair of junction implants is separated by the JFET region, the pair of junction implants is provided to a depth between 1.0 μm and 2.0 μm measured from a surface of the spreading layer opposite the drift layer, the doping concentration of the spreading layer increases as a distance from the drift layer increases, and a thickness of the spreading layer is between 1.0 μm and 2.5 μm.
2. The transistor device of claim 1 wherein the JFET region, the spreading layer, and the drift layer comprise silicon carbide.
3. The transistor device of claim 1 wherein the transistor device is a vertically disposed metal-oxide-semiconductor field-effect transistor (MOSFET).
4. The transistor device of claim 1 wherein the JFET region has a first doping concentration, the spreading layer has a second doping concentration that is different from the first doping concentration, and the drift layer has a third doping concentration that is different from the first doping concentration and the second doping concentration.
5. The transistor device of claim 4 wherein the spreading layer has a doping concentration in the range of approximately 2×10 17 cm −3 to approximately 5×10 16 cm −3 .
6. The transistor device of claim 4 wherein the JFET region has a doping concentration in the range of approximately 1×10 16 cm −3 to approximately 2×10 17 cm −3 .
7. The transistor device of claim 1 wherein a thickness of the JFET region is in the range of approximately 0.75 microns to approximately 1 micron drift layer is in the range of approximately 3.5 μm to approximately 12 μm.
8. The transistor device of claim 1 wherein a thickness of the spreading layer is in the range of approximately 1.0 microns to approximately 2.5 microns.
9. The transistor device of claim 1 wherein a thickness of the drift layer is in the range of approximately 3.5 microns to approximately 12 microns.
10. The transistor device of claim 1 wherein an internal resistance of the transistor device is less than approximately 2.2 mΩ/cm 2 .
11. The transistor device of claim 1 wherein the transistor device is adapted to support a voltage between the source and the drain of at least 600V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 1.8 mΩ/cm 2 .
12. The transistor device of claim 1 wherein the transistor device is adapted to support a voltage between the source and the drain of at least 1200V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 2.2 mΩ/cm 2 .
13. A transistor device comprising:
a substrate;
a drift layer on the substrate;
a spreading layer on the drift layer, the spreading layer having a graded doping profile such that a doping concentration of the spreading layer varies more than a factor of about 10 2 cm −3 between a JFET region and the drift layer, the doping concentration of the spreading layer increases as a distance from the drift layer increases, a thickness of the spreading layer is between 1.0 μm and 2.5 μm, and a thickness of the JFET region is between 0.75 μm and 1.5 μm; a pair of junction implants in the spreading layer and separated by the JFET region, each one of the pair of junction implants comprising a deep well region, a base region, and a source region such that a depth of the deep well region as measured from a surface of the spreading layer opposite the drift layer is between 1.0 μm and 2.0 μm; a gate contact and a source contact on the spreading layer, such that the gate contact partially overlaps and runs between each source region in the pair of junction implants; and a drain contact on the substrate opposite the drift layer.
14. The transistor device of claim 13 further comprising a gate oxide layer between the gate contact and the spreading layer.
15. The transistor device of claim 13 wherein the source contact is divided into two sections, and each section of the source contact is on a portion of the spreading layer such that each section of the source contact partially overlaps both the source region and the deep well region of each one of the pair of junction implants, respectively.
16. The transistor device of claim 13 wherein the transistor device is a vertically disposed metal-oxide-semiconductor field-effect transistor (MOSFET).
17. The transistor device of claim 13 wherein the drift layer and the spreading layer comprise silicon carbide.
18. The transistor device of claim 13 wherein a width of the JFET region is approximately 3 microns μm or less.
19. The transistor device of claim 18 wherein an internal resistance of the transistor device is less than approximately 2.2 mΩ/cm 2 .
20. The transistor device of claim 13 wherein the transistor device is adapted to support a voltage between the source contact and the drain contact of at least 600V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 1.8 mΩ/cm 2 .
21. The transistor device of claim 13 wherein the transistor device is adapted to support a voltage between the source contact and the drain contact of at least 1200V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 2.2 mΩ/cm 2 .
22. The transistor device of claim 13 wherein a thickness of the drift layer is in the range of approximately 3.5 microns to approximately 12 microns.
23. The transistor device of claim 13 wherein a thickness of the spreading layer is in the range of approximately 1.0 microns to approximately 2.5 microns.
24. The transistor device of claim 13 wherein a thickness of the JFET region is in the range of approximately 0.75 microns to approximately 1.0 microns drift layer is in a range of approximately 3.5 μm to approximately 12 μm.
25. The transistor device of claim 13 wherein a thickness of each one of the pair of junction implants is in the range of approximately 1.0 microns to approximately 2.0 microns.
26. A method for manufacturing a transistor device, the method comprising:
providing a substrate;
providing a drift layer on the substrate;
providing a spreading layer on the drift layer such that the spreading layer has a thickness between 1.0 μm and 2.5 μm and the spreading layer has a graded doping profile wherein a doping concentration of the spreading layer increases as a distance from the drift layer increases such that a ratio of the doping concentration at a surface of the spreading layer adjacent to the drift layer to the doping concentration at a surface of the spreading layer opposite the drift layer is 1:x where x is greater than or equal to 2;
providing a pair of junction implants in the spreading layer such that each of the pair of junction implants is laterally separated from one another and a depth of the pair of junction implants as measured from a surface of the spreading layer opposite the drift layer is between 1.0 μm and 2.0 μm;
providing a junction field effect transistor (JFET) region between the pair of junction implants, the JFET region having a thickness between 0.75 μm and 1.5 μm;
providing a gate oxide layer on the spreading layer opposite the drift layer;
providing a gate contact on the gate oxide layer;
providing a source contact on the spreading layer over at least one of the pair of junction implants; and
providing a drain contact on the substrate opposite the drift layer.
27. The method of claim 26 wherein the substrate, the drift layer, and the spreading layer are silicon carbide.
28. The method of claim 26 wherein x is less than or equal to 4.
29. The method of claim 26 wherein the spreading layer is provided such that the doping concentration at the surface of the spreading layer adjacent to the drift layer is 5×10 16 cm −3 and the doping concentration at the surface of the spreading layer opposite the drift layer is 2×10 17 cm −3 .
30. The method of claim 26 wherein providing the spreading layer comprises providing a plurality of layers, each having a different doping concentration to provide the graded doping profile of the spreading layer.
31. The method of claim 26 wherein the substrate, the drift layer, the spreading layer, and the pair of junction implants are provided such that a distance between the pair of junction implants is less than 3 μm, an on-state resistance of the transistor device is between 1.8 mΩ/cm 2 and 2.2 mΩ/cm 2 , and a blocking voltage of the transistor device is between 600 volts and 1200 volts.
32. The transistor device of claim 31 wherein x is less than or equal to 4.