Insulated gate bipolar transistors including current suppressing layers
View Patent ↗An insulated gate bipolar transistor (IGBT) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type. The IGBT further includes a current suppressing layer on the drift layer. The current suppressing layer has the second conductivity type and has a doping concentration that is larger than a doping concentration of the drift layer. A first conductivity type well region is in the current suppressing layer. The well region has a junction depth that is less than a thickness of the current suppressing layer, and the current suppressing layer extends laterally beneath the well region. A second conductivity type emitter region is in the well region.
1. An insulated gate bipolar transistor, comprising:
a substrate having a first conductivity type;
a drift layer on the substrate and having a second conductivity type opposite the first conductivity type;
a current suppressing layer on the drift layer, the current suppressing layer having the second conductivity type and having a doping concentration that is larger than a doping concentration of the drift layer;
a well region in the current suppressing layer and having the first conductivity type, wherein the well region has a junction depth that is less than a thickness of the current suppressing layer, and wherein the current suppressing layer extends laterally beneath the well region; and
an emitter region in the well region and having the second conductivity type;
wherein the current suppressing layer has a thickness and doping concentration that are configured to reduce current gain of a bipolar transistor portion of the transistor formed by the well region, the drift layer and the substrate, and thereby enhance carrier accumulation in a channel region of the transistor.
2. The insulated gate bipolar transistor of claim 1 , further comprising:
a gate oxide on the current suppressing layer above the well region;
a gate on the gate oxide layer; and
an emitter contact on the emitter region.
3. The insulated gate bipolar transistor of claim 1 , wherein the current suppressing layer comprises an epitaxial layer.
4. The insulated gate bipolar transistor of claim 3 , wherein the substrate comprises an off-axis n-type silicon carbide substrate, and wherein the drift layer and the current suppressing layer comprise p-type silicon carbide epitaxial layers.
5. The insulated gate bipolar transistor of claim 1 , wherein the current suppressing layer has a thickness of about 1 μm.
6. The insulated gate bipolar transistor of claim 1 , wherein the current suppressing layer has a doping concentration of about 1 ×10 15 cm −3 to about 1 ×10 17 cm −3 .
7. The insulated gate bipolar transistor of claim 6 , wherein the current suppressing layer has a doping concentration of about 1×10 16 cm −3 .
8. The insulated gate bipolar transistor of claim 6 , wherein the drift layer has a doping concentration of about 2×10 14 cm −3 to about 6×10 14 cm −3 and a thickness of about 100 μm to about 120 μm.
9. The insulated gate bipolar transistor of claim 1 , wherein the first conductivity comprises n-type and the second conductivity comprises p-type.
10. The insulated gate bipolar transistor of claim 1 , wherein the first conductivity comprises p-type and the second conductivity comprises n-type.
11. The insulated gate bipolar transistor of claim 1 , further comprising a buffer layer between the substrate and the drift layer, wherein the buffer layer has the second conductivity type.
12. The insulated gate bipolar transistor of claim 1 , wherein the well region has a junction depth of about 0.5 μm.
13. The insulated gate bipolar transistor of claim 1 ,
wherein the current suppressing layer has a thickness of about 1 μm, and
wherein the well region has a junction depth of about 0.5 μm.
14. An insulated gate bipolar transistor, comprising:
an n-type silicon carbide substrate;
a p-type silicon carbide drift layer on the n-type silicon carbide substrate;
a p-type epitaxial silicon carbide current suppressing layer on the p-type silicon carbide drift layer, the epitaxial current suppressing layer having a doping concentration that is larger than a doping concentration of the p-type silicon carbide drift layer;
an n+well region in the epitaxial current suppressing layer, wherein the n+well region has a junction depth that is less than a thickness of the epitaxial current suppressing layer; and
a p+emitter region in the n+well region;
wherein the current suppressing layer has a thickness and doping concentration that are configured to reduce current gain of a bipolar transistor portion of the transistor formed by the well region, the drift layer and the substrate, and thereby enhance hole accumulation in a channel region of the transistor.