Granted Patent B2

US 9,564,806 · App. 14/036,611 · Granted Feb 7, 2017

Abstract

Claims (47)

1. An apparatus comprising:

an input port;

an inductor having a first terminal coupled to a first terminal of the input port;

a first switch configured to couple and decouple a second terminal of the input port and a second terminal of the inductor;

at least two serially-coupled capacitors;

at least two serially-coupled second switches coupled in parallel with the first switch and configured to selectively route current from the inductor to the at least two serially-coupled capacitors; and

a control circuit configured to close the first switch to charge the inductor from a power source at the input port in spaced apart first intervals and to operate the at least two serially-coupled second switches to discharge the charged inductor directly into different individual ones of the at least two serially-coupled capacitors in respective spaced apart second intervals interspersed with the first intervals and thereby develop a voltage across a load coupled in parallel with the at least two serially-coupled capacitors.

2. The apparatus of claim 1 , wherein the control circuit is configured to operate the first switch at a higher frequency than each of the at least two serially-coupled second switches.

3. The apparatus of claim 1 , wherein the control circuit is configured to constrain switching of the at least two serially-coupled second switches to occur at about zero volts in generating the voltage across the load.

4. The apparatus of claim 1 , wherein the control circuit is configured to limit a voltage across the first switch to less than about half of the voltage across the load.

5. The apparatus of claim 1 , wherein the first switch comprises a transistor of a first type and wherein the at least two serially-coupled second switches comprise transistors of a second type.

6. The apparatus of claim 5 , wherein the first switch comprises a silicon carbide (SiC) field-effect transistor (FET) and wherein the at least two serially-coupled second switches comprise insulated gate bipolar transistors (IGBTs).

7. The apparatus of claim 1 , further comprising a rectifier circuit configured to couple the at least two serially coupled second switches to the at least two serially-coupled capacitors.

8. An apparatus comprising:

an input port;

an inductor having a first terminal coupled to a first terminal of the input port;

a first switch configured to couple and decouple a second terminal of the input port and a second terminal of the inductor;

at least two serially-coupled capacitors;

at least two serially-coupled second switches coupled in parallel with the first switch and configured to selectively route current from the inductor to the at least two serially-coupled capacitors; and

a control circuit configured to close the first switch to charge the inductor, open the first switch while a first one of the at least two serially-coupled second switches is open and a second one of the at least two serially-coupled second switches is closed to discharge the inductor to a first one of the at least two serially-coupled capacitors, close the first switch to charge the inductor again and open the first switch while the second one of the at least two serially-coupled second switches is open and the first one of the at least two serially-coupled second switches is closed to discharge the inductor to a second one of the at least two serially-coupled capacitors.

9. The apparatus of claim 8 , wherein the control circuit is configured to change states of the at least two serially-coupled second switches when the first switch is closed.

10. A boost converter comprising:

an inductor having a first terminal configured to be coupled to a power source;

an FET coupled between a second terminal of the inductor and the power source;

at least two serially-coupled capacitors configured to be coupled in parallel with a load;

at least two serially-coupled bipolar transistors coupled in parallel with the FET and configured to selectively couple the at least two serially-coupled capacitors to the inductor;

a rectifier circuit configured to couple the at least two serially-coupled bipolar transistors to the at least two serially-coupled capacitors; and

a control circuit configured to turn on the FET to charge the inductor from the power source in spaced apart first intervals and to operate the at least two serially-coupled bipolar transistors to discharge the charged inductor directly into different individual ones of the at least two serially-coupled capacitors in respective spaced apart second intervals interspersed with the first intervals and thereby develop a voltage across a load coupled in parallel with the at least two serially-coupled capacitors.

11. The boost converter of claim 10 , wherein the control circuit is configured to turn on the FET to charge the inductor, turn off the FET while a first one of the at least two serially-coupled bipolar transistors is off and a second one of the at least two serially-coupled bipolar transistors is on to discharge the inductor to a first one of the at least two serially-coupled capacitors, turn on the FET to charge the inductor again, and turn off the FET while the second one of the bipolar transistors is off and the first one of the at least two serially-coupled bipolar transistors is on to discharge the inductor to a second one of the at least two serially-coupled capacitors.

12. The boost converter of claim 10 , wherein the control circuit is configured to change states of the at least two second bipolar transistors when the FET is on.

13. The boost converter of claim 10 , wherein the control circuit is configured to delay transition of gate signals to the at least two serially-coupled bipolar transistors after transition of a gate signal to the FET for a period at least as long as about a turn-on time of the FET.

14. The boost converter of claim 10 , wherein the control circuit is configured to constrain switching of the at least two serially-coupled bipolar transistors to occur at about zero volts.

15. The boost converter of claim 10 , wherein the control circuit is configured to limit a voltage across the FET to less than about half of a voltage across the load.

16. The boost converter of claim 10 , wherein the FET comprises a SiC MOSFET.

17. The boost converter of claim 10 , wherein the at least two serially-coupled bipolar transistors comprise IGBTs.

18. A method comprising:

coupling a first terminal of an inductor to a first terminal of a power source;

coupling at least two serially-coupled capacitors in parallel with a load; and

repeatedly coupling a second terminal of the inductor to a second terminal of the power source to charge the inductor in spaced apart first intervals and decoupling the second terminal of the inductor from the second terminal of the power source to discharge the charged inductor directly into different individual ones of the at least two serially-coupled capacitors in respective spaced apart second intervals interspersed with the first intervals to generate a voltage across the load that is greater than a voltage across the power source.

19. The method of claim 18 , wherein charging the inductor comprises closing a first switch to couple the inductor in series with the power source and wherein discharging the inductor comprises opening the first switch while different ones of at least two serially-coupled second switches are open to charge different ones of the at least two serially-coupled capacitors.

20. The method of claim 19 :

wherein charging the inductor comprises closing the first switch to charge the inductor;

wherein discharging the inductor comprises opening the first switch while a first one of the at least two serially-coupled second switches is open and a second one of the at least two serially-coupled second switches is closed to discharge the inductor to a first one of the at least two serially-coupled capacitors;

wherein charging the inductor further comprises closing the first switch to charge the inductor again; and

wherein discharging the inductor further comprises opening the first switch while the second one of the at least two serially-coupled second switches is open and the first one of the at least two serially-coupled second switches is closed to discharge the inductor to a second one of the at least two serially-coupled capacitors.

21. The method of claim 18 , wherein the first switch comprises a FET and wherein the second switches comprise IGBTs.

22. The method of claim 21 , wherein the FET comprises a SiC MOSFET.

Assignments (8)