POWER SEMICONDUCTOR DIE WITH IMPROVED THERMAL PERFORMANCE
A power semiconductor die includes a substrate and a drift layer on the substrate. The drift layer includes an active area, an edge termination area surrounding the active area, and a thermal dissipation area surrounding the edge termination area. The thermal dissipation area is configured to reduce a thermal resistance of the power semiconductor die. By providing the thermal dissipation area, the operating voltage and/or current of the power semiconductor die can be increased without an increase in the active area. Further, the manufacturing yield of the power semiconductor die can be improved.
1 . A power semiconductor die comprising:
a substrate; and
a drift layer on the substrate, the drift layer comprising:
an active area;
an edge termination area surrounding the active area; and
a thermal dissipation area surrounding the edge termination area and configured to reduce a thermal resistance of the power semiconductor die.
2 . The power semiconductor die of claim 1 wherein:
the active area comprises one or more implanted regions and is configured to conduct current during a conduction mode of operation of the power semiconductor die;
the edge termination area comprises one or more implanted termination regions and is configured to reduce an electric field during a blocking mode of operation of the power semiconductor die; and
the thermal dissipation area is electrically inactive.
3 . The power semiconductor die of claim 2 wherein the thermal dissipation area does not include any implanted regions.
4 . The power semiconductor die of claim 2 wherein a ratio of the combination of the active area and the edge termination area to the combination of the active area, the edge termination area, and the thermal dissipation area is between 1:1.10 and 1:1.35.
5 . The power semiconductor die of claim 2 wherein the thermal dissipation area comprises at least 10% of a total area of the power semiconductor die and less than 35% of the total area of the power semiconductor die.
6 . The power semiconductor die of claim 2 wherein a blocking voltage of the power semiconductor die is less than 10 kV.
7 . The power semiconductor die of claim 2 wherein the substrate and the drift layer comprise a wide bandgap semiconductor material.
8 . The power semiconductor die of claim 7 wherein the wide bandgap semiconductor material comprises silicon carbide.
9 . The power semiconductor die of claim 2 wherein the one or more implanted regions in the active area provide a metal-oxide-semiconductor field-effect transistor (MOSFET).
10 . A power semiconductor die comprising:
a substrate;
a drift layer on the substrate, the drift layer comprising an active area and an edge termination area, wherein the combination of the active area and the edge termination area comprises less than 90% of a total area of the power semiconductor die, and as low as 65% of the total area of the power semiconductor die.
11 . The power semiconductor die of claim 10 wherein:
the active area comprises one or more implanted regions and is configured to conduct current during a conduction mode of operation of the power semiconductor die; and
the edge termination area comprises one or more implanted termination regions and is configured to reduce an electric field during a blocking mode of operation of the power semiconductor die.
12 . The power semiconductor die of claim 11 wherein the substrate and the drift layer comprise a wide bandgap semiconductor material.
13 . The power semiconductor die of claim 11 wherein the wide bandgap semiconductor material comprises silicon carbide.
14 . The power semiconductor die of claim 11 wherein a blocking voltage of the power semiconductor device is less than 10 kV.
15 . The power semiconductor die of claim 11 wherein the one or more implanted regions in the active area provide a metal-oxide-semiconductor field-effect transistor (MOSFET).
16 . A power module comprising:
a power substrate;
one or more power semiconductor die on the power substrate, each of the one or more power semiconductor die comprising:
a substrate; and
a drift layer on the substrate, the drift layer comprising:
an active area;
an edge termination area surrounding the active area; and
a thermal dissipation area surrounding the edge termination area and configured to reduce a thermal resistance of the power semiconductor die.
17 . The power module of claim 16 wherein for each of the one or more power semiconductor die:
the active area comprises one or more implanted regions and is configured to conduct current during a conduction mode of operation of the power semiconductor die;
the edge termination area comprises one or more implanted termination regions and is configured to reduce an electric field during a blocking mode of operation of the power semiconductor die; and
the thermal dissipation area is electrically inactive.
18 . The power module of claim 16 wherein for each of the one or more power semiconductor die, a ratio of the combination of the active area and the edge termination area to the combination of the active area, the edge termination area, and the thermal dissipation area is between 1:1.10 and 1:1.35.
19 . The power module of claim 16 wherein for each of the one or more power semiconductor die, the thermal dissipation area comprises at least 10% of a total area of the power semiconductor die, and up to 35% of the total area of the power semiconductor die.
20 . The power module of claim 16 wherein a blocking voltage of each of the one or more power semiconductor die is less than 10 kV.