Silicon carbide devices having smooth channels

1. A power device, comprising:

a p-type conductivity well region;

a buried p + conductivity region in the p-type conductivity well region;

an n + conductivity region on the buried p + conductivity region; and

a channel region of the power device adjacent the buried p + conductivity region and n + conductivity region, the channel region of the power device having a root mean square (RMS) surface roughness of less than about 1.0 Å.

2. The device of claim 1 :

wherein the p-type conductivity well region comprises a p-type silicon carbide well region;

wherein the buried p + conductivity region comprises a buried region of p + silicon carbide in the p-type silicon carbide well region; and

wherein the n + conductivity region comprises an n + region of silicon carbide on the buried region of p + silicon carbide.

3. A power device, comprising:

a p-type conductivity well region;

a buried p + conductivity region in the p-type conductivity well region;

an n + conductivity region on the buried p + conductivity region;

a channel region of the power device adjacent the buried p + conductivity region and n + conductivity region, the channel region of the power device having a root mean square (RMS) surface roughness of less than about 1.0 Å,

wherein the p-type conductivity well region comprises a p-type silicon carbide well region;

wherein the buried p + conductivity region comprises a buried region of p + silicon carbide in the p-type silicon carbide well region; and

wherein the n + conductivity region comprises an n + region of silicon carbide on the buried region of p + silicon carbide; and

a sacrificial oxide layer on a surface of the channel region having a thickness of from about 100 to about 1000 Å, wherein the RMS surface roughness of the channel region is reduced to about 0.70 Å after formation of the sacrificial oxide layer.

4. The device of claim 2 , further comprising an n − silicon carbide region on the channel region of the power device, the presence of the n − silicon carbide region providing a reduction in a surface roughness of the channel region.

5. A power device, comprising:

a p-type conductivity well region;

a buried p + conductivity region in the p-type conductivity well region;

an n + conductivity region on the buried p + conductivity region;

a channel region of the power device adjacent the buried p + conductivity region and n + conductivity region, the channel region of the power device having a root mean square (RMS) surface roughness of less than about 1.0 Å; and

an n − silicon carbide region on the channel region of the power device, the presence of the n − silicon carbide region providing a reduction in a surface roughness of the channel region,

wherein the reduction in the surface roughness is a reduction in a root mean square (RMS) surface roughness of from at least about 28 Å to less than about 1.0 Å.

6. The device of claim 4 , wherein the n − region of silicon carbide on the channel region has a thickness of from about 1000 to about 5000 Å.

7. The device of claim 6 , wherein the thickness of the n − region of silicon carbide on the channel region is about 1500 Å.

8. The device of claim 4 , wherein the n − region comprises a remaining portion of an n − epitaxial layer on the channel region after removal of a removed portion of the n − epitaxial layer.

9. The device of claim 8 , wherein the n − epitaxial layer has a thickness of from about 1500 Å to about 6000 Å before removal of the removed portion thereof.

10. The device of claim 4 , further comprising an n-type region of silicon carbide in the p-type silicon carbide well region adjacent the channel region, wherein the channel region is defined between the buried region of p + silicon carbide and the n-type region of silicon carbide and wherein the n − region only remains on the channel region.

11. The device of claim 2 , further comprising;

a silicon carbide substrate, wherein the p-type silicon carbide well region is provided on the silicon carbide substrate; and

an n − silicon carbide layer between the silicon carbide substrate and the p-type silicon carbide well region,

wherein the p-type silicon carbide well region comprises an implanted region of p-type silicon carbide in the n − silicon carbide layer;

wherein the buried region of p + silicon carbide comprises an implanted region of p + silicon carbide in the p-type silicon carbide well region; and

wherein the n + region of silicon carbide comprises an implanted n-type region in the p-type silicon carbide well region on the buried region of p + silicon carbide.

12. The device of claim 2 , further comprising:

a silicon carbide substrate, wherein the p-type silicon carbide well region is provided on the silicon carbide substrate; and

an n − silicon carbide layer between the silicon carbide substrate and the p-type silicon carbide well region,

wherein the p-type silicon carbide well region comprises a p-type epitaxial layer on the n − silicon carbide layer;

wherein the buried region of p + silicon carbide comprises an implanted region of p-type silicon carbide in the p-type silicon carbide well region; and

wherein the n + region of silicon carbide comprises an implanted region of n-type silicon carbide in the p-type silicon carbide well region on the p + region of silicon carbide.

13. The device of claim 2 , further comprising an n-type region of silicon carbide in the p-type silicon carbide well region adjacent the channel region, wherein the channel region is defined between the buried region of p + silicon carbide and the n-type region of silicon carbide and wherein the n-type region of silicon carbide is a Junction Field Effect Transistor (JFET) region of the power device.

14. The device of claim 2 , further comprising:

a silicon carbide substrate, wherein the p-type silicon carbide well region is provided on the silicon carbide substrate; and

an n − silicon carbide layer between the silicon carbide substrate and the p-type silicon carbide well region,

wherein the substrate comprises an n − substrate which serves as a drift region of the power device, the device further comprising an n + drain region on the substrate opposite the n − silicon carbide layer.

15. The device of claim 14 , wherein the n + drain region comprises an implanted n + drain region in the n − substrate or an epitaxial n + drain region on the n − substrate.

16. The device of claim 2 , wherein the power device comprises a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).

17. A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) comprising a channel region having a root mean square (RMS) surface roughness of less than about 1.0 Å.

18. A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) comprising:

a channel region having a root mean square (RMS) surface roughness of less than about 1.0 Å; and

a sacrificial oxide layer on a surface of the channel region having a thickness of from about 100 to about 1000 Å, wherein the RMS surface roughness of the channel region is reduced to about 0.70 Å after formation of the sacrificial oxide layer.

19. The MOSFET of claim 17 , further comprising an n − silicon carbide region on the channel region of the MOSFET, the presence of the n − silicon carbide region providing a reduction in a surface roughness of the channel region.

20. A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) comprising:

a channel region having a root mean square (RMS) surface roughness of less than about 1.0 Å; and

an n − silicon carbide region on the channel region of the MOSFET, the presence of the n − silicon carbide region providing a reduction in a surface roughness of the channel region,

wherein the reduction in the surface roughness is a reduction in a root mean square (RMS) surface roughness of from at least about 28 Å to less than about 1.0 Å.

21. The MOSFET of claim 19 , wherein the n − region of silicon carbide on the channel region has a thickness of from about 1000 to about 5000 Å.

22. The MOSFET of claim 21 , wherein the thickness of the n − region of silicon carbide on the channel region is about 1500 Å.

23. The MOSFET of claim 19 , wherein the n − region comprises a remaining portion of an n − epitaxial layer on the channel region after removal of a removed portion of the n − epitaxial layer.

24. The MOSFET of claim 23 , wherein the n − epitaxial layer has a thickness of from about 1500 Å to about 6000 Å before removal of the removed portion thereof.

25. The MOSFET of claim 19 , further comprising:

a silicon carbide substrate;

an n − silicon carbide layer on the silicon carbide substrate;

a p-type silicon carbide well region on the n − silicon carbide layer;

a buried region of p + silicon carbide in the p-type silicon carbide well region; and

an n + region of silicon carbide on the buried region of p + silicon carbide, wherein the channel region of the MOSFET is adjacent the buried region of p + and n + region of silicon carbide.

26. The MOSFET of claim 25 , further comprising an n-type region of silicon carbide in the p-type silicon carbide well region adjacent the channel region, wherein the channel region is defined between the buried region of p + silicon carbide and the n-type region of silicon carbide and wherein the n − region only remains on the channel region.

27. The MOSFET of claim 25 , further comprising an n-type region of silicon carbide in the p-type silicon carbide well region adjacent the channel region, wherein the channel region is defined between the buried region of p + silicon carbide and the n-type region of silicon carbide and wherein the n-type region of silicon carbide is a Junction Field Effect Transistor (JFET) region of the MOSFET.

28. The MOSFET of claim 25 , wherein the substrate comprises an n − substrate which serves as a drift region of the MOSFET, the MOSFET further comprising an n + drain region on the substrate opposite the n − silicon carbide layer.

29. The MOSFET of claim 28 , wherein the n + drain region comprises an implanted n + drain region in the n − substrate or an epitaxial n + drain region on the n − substrate.

30. A power device, comprising:

a p-type conductivity well region;

a buried p + conductivity region in the p-type conductivity well region;

an n + conductivity region on the buried p + conductivity region;

a channel region of the power device adjacent the buried p + conductivity region and n + conductivity region; and

an n − conductivity region on the channel region of the power device, the presence of the n − conductivity region providing a reduction in a surface roughness of the channel region.

31. The device of claim 30 :

wherein the p-type conductivity well region comprises a p-type silicon carbide well region;

wherein the buried p + conductivity region comprises a buried region of p + silicon carbide in the p-type silicon carbide well region;

wherein the n + conductivity region comprises an n + region of silicon carbide on the buried region of p + silicon carbide; and

wherein the n − conductivity region comprises an n − silicon carbide region.

32. The device of claim 1 , wherein the n + conductivity region is directly on the buried p + conductivity region.