Barrier Structure for Sub-100 Nanometer Gate Length Devices
Transistor devices are provided. In one example, the transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The transistor device includes a gate contact having a gate length of about 100 nm or less. A ratio of the gate length to a thickness of the multilayer barrier structure is in a range of about 8:1 to about 16:1.
1 . A transistor device, comprising:
a channel layer;
a multilayer barrier structure on the channel layer; and
a gate contact having a gate length of about 100 nm or less;
wherein a ratio of the gate length to a thickness of the multilayer barrier structure is in a range of about 8:1 to about 16:1.
2 . The transistor device of claim 1 , wherein the ratio of the gate length to the thickness of the multilayer barrier structure is in a range of about 8:1 to 12:1.
3 . The transistor device of claim 1 , wherein a two-dimensional electron gas (2DEG) at an interface between the channel layer and the multilayer barrier structure has an electron mobility in a range of about 800 cm2/Vs to about 2500 cm2/Vs.
4 . The transistor device of claim 1 , wherein a two-dimensional electron gas (2DEG) at an interface between the channel layer and the multilayer barrier structure has a carrier concentration in a range of about 1.2×10 13 cm −2 to about 2.0×10 13 cm 2 .
5 . The transistor device of claim 1 , wherein a two-dimensional electron gas (2DEG) at an interface between the channel layer and the multilayer barrier structure has a transconductance in a range of about 500 mS/mm to about 800 mS/mm.
6 . The transistor device of claim 1 , wherein the multilayer barrier structure has a peak thickness in a range of about 50 Angstroms to about 120 Angstroms.
7 . The transistor device of claim 1 , wherein the multilayer barrier structure comprises a Group III-nitride based barrier structure.
8 . The transistor device of claim 1 , wherein the multilayer barrier structure comprises a first Group III-nitride layer and a second Group III-nitride layer on the first Group III-nitride layer.
9 . The transistor device of claim 8 , wherein the first Group III-nitride layer is an Al x Ga 1-x N layer, where x≥0.75, wherein the second Group III-nitride layer is an Al y Ga 1-y N layer, where y≥0.3.
10 . The transistor device of claim 9 , wherein the first Group III-nitride layer has a thickness in a range of about in a range of about 5 Angstroms to about 15 Angstroms and the second Group III-nitride layer has a thickness in a range of about 70 Angstroms to about 100 Angstroms.
11 . The transistor device of claim 8 , wherein the first Group III-nitride layer is an Al x Ga 1-x N layer, where x≥0.75, wherein the second Group III-nitride layer is a GaN layer.
12 . The transistor device of claim 11 , wherein the first Group III-nitride layer has a thickness in a range of about 30 Angstroms to about 60 Angstroms and the second Group III-nitride layer has a thickness in a range of about 10 Angstroms to about 70 Angstroms.
13 . The transistor device of claim 7 , wherein the multilayer barrier structure comprises a plurality Group III-nitride layers arranged in an alternating manner.
14 . The transistor device of claim 1 , wherein the gate length of the gate contact is in a range of about 40 nm to about 90 nm.
15 . The transistor device of claim 1 , wherein the gate length of the gate contact is in a range of about 60 nm to about 90 nm.
16 . The transistor device of claim 1 , wherein the gate contact is recessed into the multilayer barrier structure, wherein a ratio of the gate length to a distance between the gate contact and the channel layer is in a range of about 8:1 to about 16:1.
17 . The transistor device of claim 1 , wherein the transistor device further comprises a cap layer adjacent the gate contact, wherein a ratio of the gate length to a distance between the gate contact and the channel layer is in a range of about 8:1 to about 16:1.
18 . The transistor device of claim 1 , wherein the transistor device is a high electron mobility transistor device.
19 . The transistor device of claim 1 , wherein the channel layer is on a silicon carbide substrate.
20 . A transistor device, comprising:
a channel layer;
a Group III-nitride based barrier structure on the channel layer; and
a gate contact;
wherein the Group III-nitride based barrier structure has a peak thickness of less than about 120 Angstroms.
21 . The transistor device of claim 20 , wherein a gate length of the gate contact is about 100 nm or less.
22 . The transistor device of claim 20 , wherein a gate length of the gate contact is in a range of about 60 nm to about 90 nm.
23 . The transistor device of claim 20 , wherein the peak thickness of the Group III-nitride based barrier structure is in a range of about 50 Angstroms to about 120 Angstroms.
24 . The transistor device of claim 20 , wherein the Group III-nitride based barrier structure comprises a first Group III-nitride layer and a second Group III-nitride layer on the first Group III-nitride layer
25 . The transistor device of claim 24 , wherein the first Group III-nitride layer is an Al x Ga 1-x N layer, where x≥0.75, wherein the second Group III-nitride layer is an Al y Ga 1-y N layer, where y≥0.3.
26 . The transistor device of claim 25 , wherein the first Group III-nitride layer has a thickness in a range of about in a range of about 5 Angstroms to about 15 Angstroms and the second Group III-nitride layer has a thickness in a range of about 70 Angstroms to about 100 Angstroms.
27 . A transistor device, comprising:
a channel layer;
a barrier structure on the channel layer; and
a gate contact having a gate length in a range of about 60 nm to about 100 nm;
a two-dimensional electron gas (2DEG) at an interface between the channel layer and the barrier structure, the 2DEG having an electron mobility in a range of about 800 cm2/Vs to about 2500 cm2/Vs.
28 . The transistor device of claim 27 , wherein the 2DEG at the interface between the channel layer and the barrier structure has a transconductance about 500 mS/mm to about 800 mS/mm.
29 . The transistor device of claim 27 , wherein a peak thickness of the barrier structure is in a range of about 50 Angstroms to 120 Angstroms.
30 . The transistor device of claim 27 , wherein the barrier structure comprises an AlN layer and an AlGaN layer on the AlN layer, the AlGaN layer having an aluminum mole fraction of about 30% or greater.
31 . The transistor device of claim 30 , wherein the AlN layer has a thickness in a range of 5 Angstroms to 15 Angstroms and the AlGaN layer has a thickness in a range of about 70 Angstroms to about 100 Angstroms.
32 . A transistor device, comprising:
a channel layer;
a barrier structure on the channel layer; and
a two-dimensional electron gas (2DEG) at an interface between the channel layer and the barrier structure, the 2DEG having a transconductance in a range of about 500 mS/mm to about 800 mS/mm;
wherein a peak thickness of the barrier structure is in a range of about 50 Angstroms to about 120 Angstroms.
33 . The transistor device of claim 32 , further comprising a gate contact having a gate length in a range of about 60 nm to about 90 nm;
34 . The transistor device of claim 32 , wherein the barrier structure comprises an AlN layer and an AlGaN layer on the AlN layer, the AlGaN layer having an aluminum mole fraction of about 30% or greater.
35 . The transistor device of claim 34 , wherein the AlN layer has a thickness in a range of 5 Angstroms to 15 Angstroms and the AlGaN layer has a thickness in a range of about 70 Angstroms to about 100 Angstroms.