Low 1C screw dislocation 3 inch silicon carbide wafer
View Patent ↗A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 3 inches and a 1 c screw dislocation density from about 500 cm −2 to about 2000 cm −2 .
1. A single crystal wafer of SiC having a diameter of at least about 3 inches and a 1 c screw dislocation density from about 55 cm −2 to about 2500 cm −2 .
2. A single crystal wafer of SiC according to claim 1 wherein the 1 c screw dislocation density is less than about 1500 cm −2 .
3. A single crystal wafer of SiC according to claim 1 wherein the 1 c screw dislocation density is less than about 1200 cm −2 .
4. A single crystal wafer of SiC according to claim 1 wherein the crystal has a polytype selected from the group consisting of the 3C, 4H, 6H, 2H, and 15R polytypes.
5. A single crystal wafer of SiC according to claim 1 wherein the 1 c screw dislocation density is less than about 2000 cm −2 .
6. A single crystal wafer of SiC according to claim 1 wherein the wafer is less than about 5 inches in diameter.
7. A high quality semiconductor precursor wafer comprising:
a single crystal silicon carbide wafer having a diameter of at least about 3 inches;
said wafer having the 4H polytype; and
said wafer having a 1 c screw density on its surface is from about 500 cm −2 to about 2500 cm −2 .
8. A high quality semiconductor precursor wafer according to claim 7 wherein said surface 1 c screw dislocation density represents a count of the 1 c screw dislocations on said surface following an etch that preferentially emphasizes 1 c screw dislocation defects.
9. A high quality semiconductor precursor wafer according to claim 8 wherein said surface 1 c screw dislocation density represents a count of the total 1 c screw dislocations on said surface following an etch of the surface in molten potassium hydroxide.
10. A high quality semiconductor precursor wafer comprising:
a single crystal silicon carbide wafer having a diameter of at least about 3 inches;
said wafer having the 4H polytype;
said wafer having a 1 c screw dislocation density on its surface is from about 500 cm −2 to about 2500 cm −2 ; and
a Group III-nitride layer on said surface of said silicon carbide wafer.
11. A semiconductor precursor wafer according to claim 10 wherein said Group III-nitride layer is selected from the group consisting of GaN, AlGaN, AN, AlInGaN, InN, AlInN and mixtures thereof.
12. A plurality of semiconductor device precursors comprising:
a single crystal silicon carbide wafer having a diameter of at least about 3 inches and a 1 c screw dislocation density on the surface is from about 500 cm −2 to about 2500 cm −2 ; and
a plurality of respective Group III-nitride epitaxial layers on some portions of said wafer.
13. A semiconductor wafer comprising:
a single crystal silicon carbide substrate of at least about 3 inches and having a 1 c screw dislocation density is from about 500 cm −2 to about 2500 cm −2 ; and
a plurality of devices on said silicon carbide substrate, each said device comprising:
an epitaxial layer located on the substrate, said layer having a concentration of suitable dopant atoms for making the epitaxial layer a first conductivity type, and respective source, channel, and drain portions;
a metal oxide layer on said channel portion; and
and a metal gate contact on said metal oxide layer for forming an active channel when a bias is applied to said metal gate contact.
14. A semiconductor wafer comprising:
a single crystal silicon carbide substrate of at least about 3 inches and having a 1 c screw dislocation density is from about 500 cm −2 to about 2500 cm −2 ; and
a plurality of devices on said silicon carbide substrate, each said device comprising:
a conductive channel on said substrate;
a source and a drain on said conductive channel; and
a metal gate contact between said source and said drain on said conductive channel for forming an active channel when a bias is applied to the metal gate contact.
15. A semiconductor wafer comprising:
a single crystal silicon carbide substrate of at least about 3 inches and having a 1 c screw dislocation density is from about 500 cm −2 to about 2500 cm −2 ; and
a plurality of junction field-effect transistors positioned on said single crystal silicon carbide substrate.
16. A semiconductor wafer comprising:
a single crystal silicon carbide substrate of at least about 3 inches and having a 1 c screw dislocation density is from about 500 cm −2 to about 2500 cm −2 ; and
a plurality of hetero-field effect transistors positioned on said single crystal silicon carbide substrate.
17. A semiconductor wafer comprising:
a bulk single crystal silicon carbide substrate of at least about 3 inches and having a 1 c screw dislocation density of less than 2500 cm −2 , said bulk single crystal having respective first and second surfaces opposite one another; and
a plurality of diodes positioned on said single crystal silicon carbide substrate.
18. A single crystal wafer of SiC having a diameter between about 3 inches and about 5 inches and a 1 c screw dislocation density from about 500 cm −2 to about 2500 cm −2 .
19. A single crystal wafer of SiC according to claim 18 wherein the 1 c screw dislocation density is less than about 2000 cm −2 .
20. A single crystal wafer of SiC according to claim 18 wherein the 1 c screw dislocation density is less than about 1500 cm −2 .
21. A single crystal wafer of SiC according to claim 18 wherein the 1 c screw dislocation density is less than about 1200 cm −2 .