High voltage silicon carbide MOS-bipolar devices having bi-directional blocking capabilities

1. A high voltage silicon carbide (SiC) device, comprising:

a SiC insulated gate bipolar transistor (IGBT) comprising a voltage blocking substrate as a drift region of the IGBT;

a planar edge termination structure at a first surface of the voltage blocking substrate and surrounding an active region of the IGBT;

a beveled edge termination structure extending through a second surface of the voltage blocking substrate opposite the first surface of the voltage blocking substrate, wherein the voltage blocking substrate is a boule grown substrate; and

an epitaxial silicon carbide layer formed on the second surface of the voltage blocking substrate,

wherein the planar edge termination structure includes a plurality of floating guard rings;

wherein the epitaxial silicon carbide layer has a conductivity type opposite to a conductivity type of the voltage blocking substrate; and

wherein the voltage blocking substrate includes an upper portion having a substantially vertical edge and a lower portion having a beveled edge extending to a bottom surface of the epitaxial silicon carbide layer, so as to form the beveled edge termination structure.

2. The device of claim 1 , wherein the voltage blocking substrate comprises a 4H—SiC high purity substrate having a carrier concentration no greater than about 1.0×10 15 cm −3 .

3. The device of claim 2 , wherein the voltage blocking substrate has a thickness of greater than about 100 μm.

4. The device of claim 1 , wherein the voltage blocking substrate comprises an n-type SiC substrate.

5. The device of claim 1 , wherein the voltage blocking substrate comprises a p-type SiC substrate.

6. A high voltage silicon carbide (SiC) device, comprising:

a first SiC layer having a first conductivity type on a first surface of a voltage blocking SiC substrate having a second conductivity type opposite to the first conductivity type;

a first region of SiC at a second surface of the voltage blocking substrate and having the first conductivity type;

a second region of SiC in the first region of SiC, the second region having the first conductivity type and having a carrier concentration higher than a carrier concentration of the first region;

a third region of SiC in the first region of SiC, the third region having the second conductivity type;

an insulator layer on the second surface of the voltage blocking substrate;

a gate electrode on the insulator layer and adjacent the first and third regions of SiC;

a first contact on the second and third regions of SiC;

a second contact on a bottom surface of the first SiC layer, wherein the voltage blocking substrate is a boule grown substrate;

a planar edge termination structure at the second surface of the voltage blocking substrate; and

a beveled edge termination structure at the first surface of the voltage blocking substrate opposite to the second surface of the substrate,

wherein the planar edge termination structure includes a plurality of floating guard rings; and

wherein the voltage blocking substrate includes an upper portion having a substantially vertical edge and a lower portion having a beveled edge extending to the bottom surface of the first SiC layer, so as to form the beveled edge termination structure.

7. The device of claim 6 , wherein the voltage blocking substrate comprises a 4H—SiC high purity substrate having a carrier concentration no greater than about 1.0×10 15 cm −3 .

8. The device of claim 7 , wherein the voltage blocking substrate has a thickness of greater than about 100 μm.

9. The device of claim 6 , wherein the first conductivity type comprises p-type SiC and the second conductivity type comprises n-type SiC.

10. The device of claim 6 , wherein the first conductivity type comprises n-type SiC and the second conductivity type comprises p-type SiC.

11. The device of claim 6 , wherein the first SiC layer has a thickness of from about 0.1 to about 20.0 μm.

12. The device of claim 6 , wherein the first SiC layer has a carrier concentration of from about 1×10 16 to about 1×10 21 cm −3 .

13. The device of claim 6 , wherein the first SiC region has a carrier concentration of from about 1×10 15 to about 5×10 · cm −3 .

14. The device of claim 6 , wherein the first SiC region has a depth of from about 0.3 to about 2.0 μm.

15. The device of claim 6 , wherein the second SiC region has a carrier concentration of from about 5×10 17 to about 1×10 21 cm −3 .

16. The device of claim 6 , wherein the second SiC region has a depth of from about 0.1 to about 2.0 μm.

17. The device of claim 6 , wherein the third SiC region has a carrier concentration of from about 5×10 17 to about 1×10 21 cm −3 .

18. The device of claim 6 , wherein the third SiC region has a depth of from about 0.1 to about 1.5 μm.

19. The device of claim 6 , wherein the floating guard rings have a carrier concentration of from about 5×10 17 to about 1×10 21 cm −3 .

20. The device of claim 6 , wherein the floating guard rings have a depth of from about 0.1 to about 2.0 μm.

21. The device of claim 6 , wherein the floating guard rings have the second conductivity types;

wherein the first SiC layer has a thickness of from about 0.1 to about 20.0 μm and a carrier concentration of from about 1×10 16 to about 1×10 21 cm −3 ;

wherein the first SiC region has a carrier concentration of from about 1×10 15 to about 5×10 19 cm −3 and a depth of from about 0.3 to about 2.0 μm;

wherein the second SiC region has a carrier concentration of from about 5×10 17 to about 1×10 21 cm −3 and a depth of from about 0.1 to about 2.0 μm;

wherein the third SiC region has a carrier concentration of from about 5×10 17 to about 1×10 21 cm −3 and a depth of from about 0.1 to about 1.5 μm; and

wherein the the floating guard rings have a carrier concentration of from about 5×10 17 to about 1×10 21 cm −3 and a depth of from about 0.1 to about 2.0 μm.