Lateral field effect transistor and its fabrication comprising a spacer layer above and below the channel layer
View Patent ↗A lateral field effect transistor for high switching frequencies having a source region layer ( 4 ) and a drain region layer ( 5 ) laterally spaced and of highly doped first conductivity type, a first-conductivity-type channel layer ( 6 ) of lower doping concentration extending laterally and interconnecting the source region layer ( 4 ) and the drain region layer ( 5 ). The transistor has a gate electrode ( 7 ) arranged to control the properties of the channel layer ( 6 ), and a second-conductivity-type base layer ( 8 ) arranged under the channel layer ( 6 ) at least partially overlapping the gate electrode ( 7 ) and at a lateral distance to the drain region layer ( 5 ), the highly doped second-conductivity-type base layer ( 8 ) being shorted to the source region layer ( 4 ). The transistor also has at least one of the following: a) a spacer layer ( 10 ) having semiconductor material adjacent to the channel layer ( 6 ) and located between the channel layer ( 6 ) and gate electrode ( 7 ), at least in the vicinity of the gate electrode ( 7 ), and/or b) a spacer layer ( 9 ) having semiconductor material adjacent to the channel layer ( 6 ) and located between the channel layer ( 6 ) and the second-conductivity-type base layer ( 8 ).
1. A lateral field effect transistor comprising
a source region layer ( 4 ) and a drain region layer ( 5 ) laterally spaced in at least a portion of a single plane and of a first conductivity type,
a channel layer ( 6 ) of the first-conductivity-type extending laterally and interconnecting the source region layer ( 4 ) and the drain region layer ( 5 ) for conducting a current between these layers in the on-state of the transistor,
a gate electrode ( 7 ) arranged to control the properties of the channel layer ( 6 ) to be conducting or blocking by varying the potential applied to the gate electrode ( 7 ), and
a second-conductivity-type base layer ( 8 ) arranged under the channel layer ( 6 ) at least partially overlapping the gate electrode ( 7 ) and laterally spaced from the drain region layer ( 5 ) in at least a portion of a single plane,
said second-conductivity-type base layer ( 8 ) electrically-coupled to the source region layer ( 4 ), and
a spacer layer ( 10 ) comprising semiconductor material adjacent to the channel layer ( 6 ) of separate composition and located between the channel layer ( 6 ) and gate electrode ( 7 ) at least in the vicinity of the gate electrode ( 7 ),
said spacer layer ( 10 ) and date electrode ( 7 ) on the channel layer ( 6 ).
2. A transistor according to claim 1 ,
wherein the gate electrode ( 7 ) is recessed into the spacer layer ( 10 ) located between the gate electrode ( 7 ) and the channel layer ( 6 ).
3. A transistor according to claim 1 ,
wherein the spacer layer ( 10 ) extends all the way from the source region layer ( 4 ) to the drain region layer ( 5 ).
4. A transistor according to claim 1 , wherein said layers of the transistor comprise at least one of the following semiconductor materials Silicon, Silicon Carbide, Group IIIB-nitrides, Gallium Arsenide or any other group III-V semiconductor.
5. A transistor according to claim 1 , wherein said layers of the transistor comprise any of the principal crystal polytypes of Silicon Carbide known as 6H, 4H, 2H, 3C and 15R.
6. A transistor according to claim 1 , wherein the first-conductivity-type is n-type the second conductivity type is p-type and Silicon Carbide is used as the semiconductor material constituting the layers of the transistor.
7. A transistor according to claim 1 , wherein the second-conductivity-type base layer ( 8 ) totally overlaps the gate electrode ( 7 ).
8. A transistor according to claim 1 , wherein the transistor comprises an insulation layer arranged between the gate electrode ( 7 ) and the spacer layer ( 10 ).
9. A transistor according to claim 1 , wherein the channel layer ( 6 ) is situated between (i) the gate electrode ( 7 ) and (ii) the source and drain region layers ( 4 , 5 ) and second-conductivity-type base layer ( 8 ).
10. A transistor according to claim 1 , wherein said spacer layer ( 10 ) is a low-doped n-type or p-type.
11. A transistor according to claim 1 , wherein the plane along which said source region layer ( 4 ) and drain region layer ( 5 ) are oriented is substantially parallel to a top or bottom surface of said spacer layer ( 10 ).
12. A transistor according to claim 1 , wherein the channel layer ( 6 ) and spacer layer ( 10 ) contact both the source ( 4 ) and drain ( 5 ) region layers.
13. A transistor according to claim 1 , wherein said gate electrode ( 7 ), spacer layer ( 10 ) and channel layer ( 6 ) are stacked upon one another.
14. A lateral field effect transistor comprising
a source region layer ( 4 ) and a drain region layer ( 5 ) laterally spaced in at least a portion of a single plane and of a first conductivity type,
a channel layer ( 6 ) of the first-conductivity-type extending laterally and interconnecting the source region layer ( 4 ) and the drain region layer ( 5 ) for conducting a current between these layers in the on-state of the transistor,
a gate electrode ( 7 ) arranged to control the properties of the channel layer ( 6 ) to be conducting or blocking by varying the potential applied to the gate electrode ( 7 ), and
a second-conductivity-type base layer ( 8 ) arranged under the channel layer ( 6 ) at least partially overlapping the gate electrode ( 7 ) and laterally spaced from the drain region layer ( 5 ) in at least a portion of a single plane,
said second-conductivity-type base layer ( 8 ) directly electrically-coupled to the source region layer ( 4 ), and
a spacer layer ( 9 ) comprising semiconductor material adjacent to the channel layer ( 6 ) of separate composition and located between the channel layer ( 6 ) and the second-conductivity-type base layer ( 8 ) and being vertically-aligned at least in the vicinity of the gate electrode ( 7 ),
said spacer layer ( 9 ) on the second-conductivity type base layer ( 8 ), said channel layer ( 6 ) on the spacer layer ( 9 ), and said ate electrode ( 7 ) on the channel layer ( 6 ).
15. A transistor according to claim 14 , wherein the plane along which said source region layer ( 4 ) and drain region layer ( 5 ) are oriented is substantially parallel to a top or bottom surface of said spacer layer ( 9 ).
16. A transistor according to claim 14 , wherein said spacer layer ( 9 ) is a low-doped layer.
17. A transistor according to claim 16 , wherein said spacer layer ( 9 ) is a low-doped n-type or p-type.
18. A transistor according to claim 14 , wherein the channel layer ( 6 ) and spacer layer ( 9 ) contact both the source ( 4 ) and drain ( 5 ) region layers.
19. A transistor according to claim 14 , wherein said channel layer ( 6 ), spacer layer ( 9 ) and second-conductivity type base layer ( 8 ) are stacked upon one another underneath said gate electrode ( 7 ).
20. A transistor according to claim 14 , wherein the spacer layer ( 9 ) extends from the second-conductivity-type base layer ( 8 ) to the drain region layer ( 5 ).
21. A lateral field effect transistor comprising
a source region layer ( 4 ) and a drain region layer ( 5 ) laterally spaced in at least a portion of a single plane and of a first conductivity type,
a channel layer ( 6 ) of the first-conductivity-type extending laterally and interconnecting the source region layer ( 4 ) and the drain region layer ( 5 ) for conducting a current between these layers in the on-state of the transistor,
a gate electrode ( 7 ) arranged to control the properties of the channel layer ( 6 ) to be conducting or blocking by varying the potential applied to the gate electrode ( 7 ), and
a second-conductivity-type base layer ( 8 ) arranged under the channel layer ( 6 ) at least partially overlapping the gate electrode ( 7 ) and laterally spaced from the drain region layer ( 5 ) in at least a portion of a single plane, said second-conductivity-type base layer ( 8 ) electrically-coupled to the source region layer ( 4 ),
a first spacer layer ( 10 ) comprising semiconductor material adjacent to the channel layer ( 6 ) of separate composition and located between the channel layer ( 6 ) and gate electrode ( 7 ) at least in the vicinity of the gate electrode ( 7 ), and
a second spacer layer ( 9 ) comprising semiconductor material adjacent to the channel layer ( 6 ) of separate composition and located between the channel layer ( 6 ) and second-conductivity-type base layer ( 8 ) at least the vicinity of the gate electrode ( 7 ),
said first spacer layer ( 10 ) and gate electrode ( 7 ) on the channel layer ( 6 ),
said second spacer layer ( 9 ) on said base layer ( 8 ), and
said channel layer 6 on said second spacer layer ( 9 ).
22. A transistor according to claim 21 , wherein the plane along which said source region layer ( 4 ) and drain region layer ( 5 ) are oriented is substantially parallel to a top or bottom surface of one of said spacer layers ( 9 , 10 ).
23. A transistor according to claim 21 , wherein said spacer layers ( 9 , 10 ) are low-doped.
24. A transistor according to claim 23 , wherein said spacer layers ( 9 , 10 ) are low-doped n-type or p-type.
25. A transistor according to claim 21 , wherein the channel layer ( 6 ) and spacer layers ( 9 , 10 ) contact both the source ( 4 ) and drain ( 5 ) region layers.
26. A transistor according to claim 21 , wherein said gate electrode ( 7 ), first spacer layer ( 10 ), channel layer ( 6 ), second spacer layer ( 9 ) and second-conductivity type base layer ( 8 ) are stacked upon one another.
27. A transistor according to claim 21 , wherein the second spacer layer ( 9 ) located between the channel layer ( 6 ) and the second conductivity-type base layer ( 8 ) is thicker than the first spacer layer ( 10 ) located between the channel layer ( 6 ) and gate electrode ( 7 ).
28. A transistor according to claim 24 , wherein the doping concentration of the channel layer ( 6 ) is higher than the doping concentration of the spacer layers ( 9 , 10 ).
29. A method for producing a lateral field effect transistor according to claim 21 , and comprising the steps of
forming a the second spacer layer ( 9 ) on top of a patterned second-conductivity-type base layer ( 8 ), i.e. a base layer with a restricted lateral extension,
forming the first-conductivity-type channel layer ( 6 ) on top of the second spacer layer ( 9 ), and
forming the first spacer layer ( 10 ) on top of the first-conductivity-type channel layer ( 6 ), at least in the vicinity of the position in which the gate electrode ( 7 ) is subsequently formed.
30. A method according to claim 29 , wherein the spacer layers ( 9 , 10 ) and the patterned second-conductivity-type base layer ( 8 ) are epitaxially grown.