Trench cut light emitting diodes and methods of fabricating same
View Patent ↗A method is provided for forming semiconductor devices using a semiconductor substrate having first and second opposed sides, and at least one device layer on the second side of the substrate, the at least one device layer including first and second device portions. A first trench is formed in the first side of the substrate between the first and second device portions. A second trench is formed in the second side of the substrate between the first and second device portions.
1. A semiconductor substrate assembly comprising:
a) a semiconductor substrate having first and second opposed sides;
b) at least one device layer on the second side of the substrate, the at least one device layer including first and second device portions;
c) a first trench in the first side of the substrate between the first and second device portions; and
d) a second trench in the second side of the substrate between the first and second device portions;
e) first and second contacts on the first and second device portions, respectively; and
f) third and fourth contacts on the first side of the substrate opposite the first and second contacts, respectively.
2. The assembly of claim 1 including first and second dies separated by the first and second trenches, the first die including a first portion of the substrate and the first device portion, and the second die including a second portion of the substrate and the second device portion.
3. The assembly of claim 2 wherein the first and second dies include first and second light emitting diodes (LEDs), respectively, and/or first and second laser diodes, respectively.
4. The assembly of claim 1 wherein the second trench is substantially aligned with the first trench.
5. The assembly of claim 1 further including an isolation trench in the at least one device layer, the isolation trench defining a first mesa including the first device portion and a second mesa including the second device portion.
6. The assembly of claim 5 wherein the second trench is disposed within the isolation trench.
7. The assembly of claim 6 including an electrically insulating passivation layer on exposed surfaces of the first and second mesas and the substrate along the second trench.
8. The assembly of claim 1 wherein the first trench is ATON-shaped.
9. The assembly of claim 1 wherein the second trench has a depth in the substrate of at least about 2 μm and a width in the substrate of at least about 2 μm.
10. The assembly of claim 1 wherein the second trench has a depth in the substrate of at least about 1% of the thickness of the substrate.
11. The assembly of claim 1 wherein the first trench has a depth in the substrate of at least about 100 μm.
12. The assembly of claim 1 wherein the depth of the second trench within the substrate is between about 5 and 10% of the depth of the first trench within the substrate.
13. The assembly of claim 1 wherein the substrate is formed of a material selected from the group consisting of SiC, GaAs, GaP, sapphire and combinations thereof.
14. The assembly of claim 1 wherein the at least one device layer includes a Group III nitride.
15. A semiconductor substrate assembly comprising:
a) a semiconductor substrate having a device side;
b) at least one device layer on the device side of the substrate, the at least one device layer including first and second device portions;
c) an isolation trench in the at least one device layer, the isolation trench defining a first mesa including the first device portion and a second mesa including the second device portion;
d) a second trench in the device side of the substrate in and along the isolation trench, the second trench extending between the first and second device portions; and
e) a shaping trench in a side of the substrate opposite the device side;
f) first and second contacts on the first and second device portions, respectively; and
g) third and fourth contacts on a side of the substrate opposite the device side such that the third and fourth contacts are located opposite the first and second contacts, respectively.
16. The assembly of claim 15 including first and second dies separated by the first and second trenches, the first die including a first portion of the substrate and the first device portion, and the second die including a second portion of the substrate and the second device portion.
17. The assembly of claim 16 wherein the first and second dies include first and second light emitting diodes (LEDs), respectively, and/or first and second laser diodes, respectively.
18. The assembly of claim 15 including an electrically insulating passivation layer on exposed surfaces of the first and second mesas and the substrate along the second trench.
19. The assembly of claim 15 wherein the shaping trench is substantially aligned with the second trench.
20. The assembly of claim 15 wherein the second trench has a depth in the substrate of at least about 2 μm and a width in the substrate of at least about 2 μm.
21. The assembly of claim 15 wherein the second trench has a depth in the substrate of at least about 1% of the thickness of the substrate.
22. The assembly of claim 15 wherein the substrate is formed of a material selected from the group consisting of SiC, GaAs, GaP, sapphire and combinations thereof.
23. The assembly of claim 15 wherein the at least one device layer includes a Group III nitride.