Large area, uniformly low dislocation density GaN substrate and process for making the same
View Patent ↗Large area single crystal III-V nitride material having an area of at least 2 cm 2 , having a uniformly low dislocation density not exceeding 3×10 6 dislocations per cm 2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 10 2 pits/cm 2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.
1. Large area single crystal III-V nitride material having an area of at least 2 cm 2 , having an average dislocation density not exceeding 3×10 6 dislocations per cm 2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns.
2. Material according to claim 1 , selected from the group consisting of AlN, InN, GaN, AlInN, AlInGaN, InGaN, and AlGaN.
3. GaN material according to claim 1 .
4. Material according to claim 1 , doped with a dopant species.
5. Material according to claim 4 , of a p-doped, n-doped or semi-insulatively doped character.
6. Material according to claim 1 , having a large area of greater than 15 cm 2 .
7. Material according to claim 1 , having a thickness of at least 0.1 mm.
8. Material according to claim 1 , having an average dislocation density not exceeding 1×10 6 cm −2 .
9. Material according to claim 1 , having a dislocation density standard deviation ratio of less than 50%.
10. Material according to claim 1 , having a dislocation density standard deviation ratio of less than 25%.
11. Material according to claim 1 , having a large area of greater than 15 cm 2 , a thickness of at least 0.1 mm, an average dislocation density not exceeding 1×10 6 cm−2, and a dislocation density standard deviation ratio of less than 25%.
12. Material according to claim 1 , wherein the plurality of distinct regions having elevated impurity concentration is disposed on an outer surface of said material.
13. Material according to claim 1 , wherein said impurity comprises any of oxygen and silicon.
14. Material according to claim 1 , wherein said plurality of distinct regions having elevated impurity concentration covers at least 50% of the growth surface area.
15. Material according to claim 1 , having a growth surface with a pit density not exceeding 3 pits/cm 2 .
16. Material according to claim 1 , having a pit-free growth surface.
17. A wafer comprising the material of claim 1 .
18. The wafer of claim 17 , having a diameter of from 5 cm to 20 cm.
19. The wafer of claim 17 , having at least one face thereof polished to a mirror finish.
20. The wafer of claim 17 , including a chemical mechanically polished gallium-terminated face.
21. The wafer of claim 17 , having a surface disposed at an angle relative to the c-plane of the III-V nitride crystal, wherein said angle is in a range of from about 0.1 to about 10 degrees.
22. The wafer of claim 17 , having at least one epitaxial layer thereon.
23. An electronic device article, including a wafer according to claim 17 and an electronic device structure fabricated on said wafer.
24. The electronic device article of claim 23 , wherein the electronic device structure includes a laser diode.
25. The electronic device article of claim 23 , wherein the electronic device structure includes a light-emitting diode.
26. The electronic device article of claim 23 , wherein the electronic device structure includes a high electron mobility transistor.
27. The electronic device article of claim 23 , wherein the electronic device structure comprises any of an integrated circuit and an optoelectronic device.
28. A wafer comprising the material of claim 1 , wherein the III-V nitride material comprises single crystal gallium nitride and the wafer includes a surface off-cut at an angle in a range of from about 0.2 to about 8 degrees toward 11-20 or 10-10 from a c-plane of said single crystal gallium nitride material.