Wide bandgap transistor devices with field plates
View Patent ↗A transistor structure comprising an active semiconductor layer with metal source and drain contacts formed in electrical contact with the active layer. A gate contact is formed between the source and drain contacts for modulating electric fields within the active layer. A spacer layer is formed above the active layer and a conductive field plate formed above the spacer layer, extending a distance L f from the edge of the gate contact toward the drain contact. The field plate is electrically connected to the gate contact and provides a reduction in the peak operational electric field.
1. A transistor, comprising:
a plurality of active semiconductor layers;
a source contact in electrical contact with said plurality of active layers;
a drain contact also in electrical contact with said plurality of active layers with space between said source contact and said drain contact on the topmost of said plurality of active layers;
a gate in electrical contact with said topmost of said plurality of active layers, between said source and drain contacts;
a spacer layer comprising a monocrystalline material on the surface of the topmost of said plurality of active layers, between said gate and said drain contact; and
a field plate directly on said spacer layer integral to said gate, said field plate providing a reduction in the peak operational electric field.
2. The transistor of claim 1 , wherein said field plate extends on said spacer layer a distance L f from the edge of said gate toward said drain contact.
3. The transistor of claim 1 , wherein said spacer layer comprises a plurality of spacer layers in a step arrangement between said gate and said drain contact.
4. The transistor of claim 3 , wherein said field plate is formed on said spacer layer step arrangement, said field plate comprising a plurality of field plate portions, each of which has a different distance between it and the topmost of said plurality of active layers.
5. The transistor of claim 1 , comprising a high electron mobility transistor (HEMT) and wherein said plurality of active layers comprises at least a buffer layer on a substrate and a barrier layer on said buffer layer with a two dimensional electron gas between said buffer and barrier layer, said barrier layer being the topmost of said plurality of active layers.
6. The transistor of claim 1 , wherein said active semiconductors layers are gallium nitride based.
7. The transistor of claim 5 , further comprising a nucleation layer between that said buffer layer and said substrate.
8. The transistor of claim 1 , comprising a metal semiconductor field effect transistor (MESFET) wherein said plurality of active layers comprises at least a buffer layer on said substrate and a channel layer on said buffer layer, said channel layer being the topmost of said plurality of active layers.
9. The transistor of claim 8 , wherein said MESFET is silicon carbide based.
10. The transistor of claim 1 , wherein said gate is gamma shaped.
11. The transistor of claim 1 , wherein said gate is at least partially recessed in said topmost of said plurality of active layers.
12. The transistor of claim 1 , further comprising a passivation layer covering the at least some of the exposed surfaces of said transistor.
13. The transistor of claim 1 , further comprising a second spacer layer covering said field plate and the surface of said spacer layer between said field plate and drain contact, and further comprising a second field plate on said second spacer layer and extending from the edge of said gate toward said drain contact.
14. The transistor of claim 1 , further comprising at least one additional spacer layer and field plate pair over said spacer layer and field plate.
15. A transistor structure, comprising:
an active Group-III nitride semiconductor layer;
metal source and drain contacts in electrical contact with said active layer;
a gate contact on said active layer between said source and drain contacts for modulating electric fields within said active layer;
a spacer layer comprising a monocrystalline material on and covering the active layer between said gate and said source and drain electrodes; and
a conductive field plate directly on said spacer layer and extending a distance from the edge of said gate contact toward said drain contact, said field plate electrically connected to said gate contact.
16. The transistor structure of claim 15 , wherein said field plate provides a reduction in the peak operational electric field compared to a transistor having a similar structure without said field plate.
17. The transistor structure of claim 15 , wherein said spacer layer comprises a layer of undoped or depleted wide bandgap material or a combination of said wide bandgap material and a dielectric material.