IP Library Granted Patent US 7,842,549
Granted Patent B2
US 7,842,549 · App. 12/195,700 · Granted Nov 30, 2010

Methods of fabricating silicon carbide devices incorporating multiple floating guard ring edge terminations

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Quick Facts
Patent No.
US 7,842,549
App. No.
12/195,700
Granted
Nov 30, 2010
Kind
B2
Abstract

Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on the floating guard rings and a silicon carbide surface charge compensation region is provided between the floating guard rings and is adjacent the insulating layer. Methods of fabricating such edge termination are also provided.

Claims (26)

1. A method of fabricating an edge termination structure for a silicon carbide semiconductor device, comprising:

providing at least two spaced apart floating guard rings in a silicon carbide layer adjacent at least a portion of a silicon carbide-based semiconductor junction;

providing an insulating layer on the floating guard rings; and

providing a silicon carbide surface charge compensation region between the floating guard rings and adjacent the insulating layer, wherein the surface charge compensation region extends completely between adjacent ones of the floating guard rings, and wherein the surface charge compensation region has a dopant concentration such that the surface of the surface charge compensation region adjacent the insulating layer is partially depleted by surface charges of the insulating layer and fully depleted when a reverse bias lower than the blocking voltage of the device is applied to the device.

2. The method of claim 1 , wherein providing a plurality of floating guard rings comprises forming a plurality of floating guard rings that extend a first distance into the silicon carbide layer and wherein providing a silicon carbide surface charge compensation region comprises forming a surface charge compensation region that extends a second distance into the silicon carbide layer, the second distance being less than the first distance.

3. The method of claim 1 , wherein the surface charge compensation region is lighter doped than the guard rings.

4. The method of claim 1 , wherein forming a silicon carbide surface charge compensation region comprises implanting regions in the silicon carbide layer.

5. The method of claim 1 , wherein the surface charge compensation region comprises a plurality of surface charge compensation regions.

6. The method of claim 1 , wherein the surface charge compensation region has a surface charge of from about 1×10 12 to about 7×10 12 cm −2 .

7. The method of claim 1 , wherein the surface charge compensation region extends a distance of from about 0.1 μm to about 2.0 μm into the silicon carbide layer.

8. The method of claim 1 , wherein the silicon carbide layer has a first conductivity type, and wherein the floating guard rings and the silicon carbide surface charge compensation region have a second conductivity type, opposite the first conductivity type.

9. A method of fabricating an edge termination structure for a silicon carbide semiconductor device, comprising:

providing a plurality of spaced apart concentric floating guard rings in a silicon carbide layer that surround at least a portion of a silicon carbide-based semiconductor junction;

providing an insulating layer on the floating guard rings; and

providing a silicon carbide surface charge compensation region between the floating guard rings and adjacent the insulating layer, wherein the surface charge compensation region comprises a single region that overlaps the floating guard rings, and wherein the surface charge compensation region has a dopant concentration such that the surface of the surface charge compensation region adjacent the insulating layer is partially depleted by surface charges of the insulating layer and fully depleted when a reverse bias lower than the blocking voltage of the device is applied to the device.

10. The method of claim 9 , wherein providing a plurality of floating guard rings comprises forming a plurality of floating guard rings that extend a first distance into the silicon carbide layer and wherein providing a silicon carbide surface charge compensation region comprises forming a surface charge compensation region that extends a second distance into the silicon carbide layer, the second distance being less than the first distance.

11. The method of claim 9 , wherein the surface charge compensation region is lighter doped than the guard rings.

12. The method of claim 9 , wherein providing a silicon carbide surface charge compensation region comprises implanting regions in the silicon carbide layer.

13. The method of claim 9 , wherein the surface charge compensation region comprises a plurality of surface charge compensation regions.

14. The method of claim 9 , wherein the surface charge compensation region has a surface charge of from about 1×10 12 to about 7×10 12 cm −2 .

15. The method of claim 9 , wherein the surface charge compensation region extends a distance of from about 0.1 μm to about 2.0 μm into the silicon carbide layer.

16. The method of claim 9 , wherein the silicon carbide layer has a first conductivity type, and wherein the floating guard rings and the silicon carbide surface charge compensation region have a second conductivity type, opposite the first conductivity type.

17. A method of fabricating an edge termination structure for a silicon carbide semiconductor device, comprising:

providing a floating guard ring in a silicon carbide layer adjacent at least a portion of a silicon carbide-based semiconductor junction;

providing an insulating layer on the floating guard ring; and

providing a silicon carbide surface charge compensation region between the junction and the floating guard ring and adjacent the insulating layer, wherein the surface charge compensation region extends completely between the junction and the floating guard ring, and wherein the surface charge compensation region has a dopant concentration such that the surface of the surface charge compensation region adjacent the insulating layer is partially depleted by surface charges of the insulating layer and fully depleted when a reverse bias lower than the blocking voltage of the device is applied to the device.

Assignments (2)
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL AT REEL/FRAME NO. 64185/0755 Recorded Sep 30, 2025
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WOLFSPEED, INC.
Reel/Frame 072989/0001 →
SECURITY INTEREST Recorded Jun 30, 2023
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
Reel/Frame 064185/0755 →