Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors

1. A silicon carbide metal-oxide semiconductor field effect transistor unit cell, comprising:

an n-type silicon carbide drift layer;

a first p-type silicon carbide region in close proximity to the drift layer;

a first n-type silicon carbide region within the first p-type silicon carbide region;

an oxide layer on the drift layer, the first p-type silicon carbide region, and the first n-type silicon carbide region; and

an n-type silicon carbide limiting region disposed between the drift layer and the first p-type silicon carbide region, wherein the n-type limiting region comprises a first portion disposed in close proximity to a floor of the first p-type silicon carbide region and a second portion disposed in close proximity to a sidewall of the first p-type silicon carbide region, wherein the n-type limiting region has a carrier concentration that is greater than a carrier concentration of the drift layer and wherein the first portion has a carrier concentration greater than a carrier concentration of the second portion.

2. A silicon carbide metal-oxide semiconductor field effect transistor unit cell according to claim 1 , wherein the first p-type silicon carbide region is implanted with aluminum.

3. A silicon carbide metal-oxide semiconductor field effect transistor unit cell according to claim 1 , wherein the n-type limiting region has a thickness of from about 0.5 μm to about 1.5 μm and a carrier concentration of from about 1×10 15 to about 5×10 17 cm −3 .

4. A silicon carbide metal-oxide semiconductor field effect transistor unit cell according to claim 1 , wherein the n-type limiting region comprises an implanted n-type region in the drift layer.

5. A silicon carbide metal-oxide semiconductor field effect transistor unit cell according to claim 1 , further comprising a second p-type silicon carbide region disposed within the first p-type silicon carbide region and adjacent the first n-type silicon carbide region.

6. A silicon carbide metal-oxide semiconductor field effect transistor unit cell according to claim 1 , wherein the n-type limiting region comprises an pitaxial layer of silicon carbide on the n-type silicon carbide drift layer.

7. A silicon carbide metal-oxide semiconductor field effect transistor unit cell according to claim 6 , wherein the first p-type region is disposed in but not through the epitaxial layer of silicon carbide.

8. A silicon carbide metal-oxide semiconductor field effect transistor unit cell according to claim 1 , further comprising:

a gate contact on the oxide layer;

a source contact on the first n-type silicon carbide region; and

a drain contact on the drift layer opposite the oxide layer.

9. A silicon carbide metal-oxide semiconductor field effect transistor unit cell according to claim 8 , wherein the gate contact comprises polysilicon or metal.

10. A silicon carbide metal-oxide semiconductor field effect transistor unit cell according to claim 8 , further comprising an n-type silicon carbide substrate disposed between the drift layer and the drain contact.

11. A silicon carbide metal-oxide semiconductor field effect transistor unit cell, comprising:

an n-type silicon carbide drift layer;

a first p-type silicon carbide region adjacent the drift layer;

a first n-type silicon carbide region within the first p-type silicon carbide region;

an oxide layer on the drift layer, the first p-type silicon carbide region, and the first n-type silicon carbide region;

an n-type silicon carbide limiting region disposed between the drift layer and a portion of the first p-type silicon carbide region, wherein the n-type limiting region has a carrier concentration that is greater than a carrier concentration of the drift layer; and

an n-type epitaxial layer on the first p-type silicon carbide region and a portion of the first n-type region, and disposed between the first n-type silicon carbide region and the first p-type silicon carbide region and the oxide layer.

12. A silicon carbide metal-oxide semiconductor field effect transistor, comprising:

a drift layer of n-type silicon carbide; first regions of p-type silicon carbide in close proximity to the drift layer;

a first region of n-type silicon carbide disposed between peripheral edges of the first regions of p-type silicon carbide;

second regions of n-type silicon carbide within the first regions of p-type silicon carbide, wherein the second regions of n-type silicon carbide have a carrier concentration greater than a carrier concentration of the drift layer and are spaced apart from the peripheral edges of the first regions of p-type silicon carbide;

an oxide layer on the drift layer, the first region of n-type silicon carbide and the second regions of n-type silicon carbide;

third regions of n-type silicon carbide disposed beneath the first regions of p-type silicon carbide and between the first regions of p-type silicon carbide and the drift layer, wherein the third regions of n-type silicon carbide have a carrier concentration greater than the carrier concentration of the drift layer, and wherein the first region of n-type silicon carbide has a higher carrier concentration than a carrier concentration of the drift layer and has a lower carrier concentration than the carrier concentration of the third regions of n-type silicon carbide;

source contacts on portions of the second regions of n-type silicon carbide;

a gate contact on the oxide layer; and

a drain contact on the drift layer opposite the oxide layer.

13. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 12 , wherein the third regions of n-type silicon carbide are adjacent the peripheral edges of the first regions of p-type silicon carbide.

14. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 12 , wherein the first region of n-type silicon carbide and the third regions of n-type silicon carbide comprise an n-type silicon carbide epitaxial layer on the drift layer, and wherein the first regions of p-type silicon carbide are formed in the n-type silicon carbide epitaxial layer.

15. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 12 , wherein the first region of n-type silicon carbide comprises a region of the drift layer.

16. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 15 , wherein the third regions of n-type silicon carbide comprise implanted n-type regions in the drift layer.

17. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 12 , further comprising an n-type epitaxial layer of silicon carbide on the first p-type regions and the first region of n-type silicon carbide.

18. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 12 , further comprising an n-type silicon carbide layer between the drift layer and the drain contact, wherein the n-type silicon carbide layer has a higher carrier concentration than the carrier concentration of the drift layer.

19. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 18 , wherein the n-type silicon carbide layer comprises an n-type silicon carbide substrate.

20. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 12 , further comprising second p-type silicon carbide regions disposed within the first p-type silicon carbide regions.

21. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 12 , wherein the third regions of n-type silicon carbide have a thickness of from about 0.5 μm to about 1.5 μm.

22. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 12 , wherein the third regions of n-type silicon carbide have a carrier concentration of from about 1×10 15 to about 5×10 17 cm −3 .

23. A silicon carbide metal-oxide semiconductor field effect transistor comprising:

an n-type silicon carbide drift layer;

spaced apart p-type silicon carbide well regions; and

an n-type silicon carbide limiting region disposed between the well regions and the drift layer, wherein the n-type limiting region comprises a first portion disposed in close proximity to respective floors of the well regions and a second portion disposed in close proximity to respective sidewalls of the well regions, and wherein the first portion has a carrier concentration greater than a carrier concentration of the second portion.

24. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 23 , wherein the n-type limiting region has a carrier concentration higher than a carrier concentration of the drift layer.

25. A silicon carbide metal-oxide semiconductor field effect transistor according to claim 23 , wherein the n-type limiting region comprises an epitaxial layer of silicon carbide on the drift layer, and wherein the p-type well regions are disposed in but not through the epitaxial layer.