Method to reduce stacking fault nucleation sites and reduce V
View Patent ↗A method is disclosed for preparing a substrate and epilayer for reducing stacking fault nucleation and reducing forward voltage (V f ) drift in silicon carbide-based bipolar devices. The method includes the steps of etching the surface of a silicon carbide substrate with a nonselective etch to remove both surface and subsurface damage, thereafter etching the same surface with a selective etch to thereby develop etch-generated structures from at least any basal plane dislocation reaching the substrate surface that will thereafter tend to either terminate or propagate as threading defects during subsequent epilayer growth on the substrate surface, and thereafter growing a first epitaxial layer of silicon carbide on the twice-etched surface.
1. A method of preparing a substrate for reducing stacking fault nucleation and reducing forward voltage (V f ) drift in silicon carbide-based bipolar devices, the method comprising:
conducting a selective etch on the surface of a silicon carbide substrate sufficient to delineate the basal plane dislocations with the wafer surface and that will thereafter tend to terminate or to propagate as threading defects while avoiding creating beta (3C) inclusions and carrot defects;
growing a conductive epitaxial layer on the selectively etched substrate surface with a sufficient thickness to support additional polishing and etching steps above the substrate;
polishing away a sufficient portion of the conductive epitaxial layer to remove the material containing the etched pits to thereby provide a surface with fewer etched pits than the surface of the selectively-etched substrate; and
thereafter conducting a non-selective etch of the epilayer sufficient to remove subsurface damage from the step of polishing the epitaxial layer but without reaching the underlying substrate, to thereby reduce the number of subsurface defects that can propagate stacking faults under forward voltage in a device formed on the substrate and the polished epilayer.
2. A substrate-preparation method according to claim 1 comprising selectively etching the surface with a molten salt.
3. A substrate-preparation method according to claim 2 comprising etching the surface with a molten salt selected from the group consisting of potassium hydroxide, mixtures of potassium hydroxide and sodium hydroxide, and a eutectic mixture of potassium hydroxide and sodium hydroxide.
4. A substrate-preparation method according to claim 1 further comprising forming a bipolar device by:
forming a n-type epitaxial layer above the polished and etched surface of the epitaxial layer; and
forming a p-type epitaxial layer above the polished and etched surface of the epitaxial layer, with a p-n junction between the n-type and p-type epitaxial layers.
5. A device-preparation method according to claim 4 comprising:
etching an n-type silicon carbide substrate;
growing, polishing and etching an n-type epitaxial layer on the selectively etched substrate surface;
growing another n-type epitaxial layer above the polished and etched epitaxial layer; and
growing a p-type epitaxial layer above the n-type epitaxial layer, with a p-n junction between the n-type and p-type epitaxial layers.
6. A method according to claim 1 comprising growing a first device epitaxial layer immediately on the surface prepared by the non-selective etch.
7. A method according to claim 1 comprising etching a single crystal silicon carbide substrate having a polytype selected from the 3C, 4H, 6H and 15R polytypes of silicon carbide.
8. A method of preparing a substrate and epilayer for reducing stacking fault nucleation and reducing forward voltage (V f ) drift in silicon carbide-based bipolar devices, the method comprising:
selectively etching the surface of a silicon carbide substrate to thereby develop etch-generated structures from at least any basal plane dislocations on the substrate that will thereafter tend to either terminate or to propagate as threading dislocations during subsequent epilayer growth on the substrate surface; and thereafter
growing a first epitaxial layer of silicon carbide on the selectively-etched surface.
9. A method according to claim 8 comprising etching the surface with a molten salt as the selective etch.
10. A method according to claim 9 comprising etching the surface with a molten salt selected from the group consisting of potassium hydroxide, mixtures of potassium hydroxide and sodium hydroxide, and a eutectic mixture of potassium hydroxide and sodium hydroxide.
11. A method according to claim 8 comprising growing a conductive epitaxial layer on the selectively-etched surface.
12. A method according to claim 10 comprising growing an n-type epitaxial layer on the selectively-etched surface.
13. A method according to claim 8 comprising growing a second conductive epilayer above the first conductive epilayer and having the opposite conductivity type from the first conductive epilayer.
14. A method according to claim 8 wherein the step of growing the first epitaxial layer comprises forming a semi-sacrificial epitaxial layer on the selectively etched surface to encourage the etched basal plane defects to reorient during subsequent growth into threaded defects;
and further comprising the steps of:
polishing the etched semi-sacrificial epitaxial layer to reduce etch pits; and
etching the polished semi-sacrificial epitaxial layer to remove subsurface damage from the step of polishing the epitaxial layer but without reaching the underlying substrate, to thereby reduce the number of subsurface defects that can propagate stacking faults under forward voltage in a device formed on the substrate and the polished epilayer;
all prior to forming the first epitaxial layer.
15. A method according to claim 14 comprising forming the semi-sacrificial layer by chemical vapor deposition.
16. A method according to claim 14 comprising polishing the etched semi-sacrificial epitaxial layer using a chemical-mechanical process.
17. A method according to claim 14 comprising etching the polished semi-sacrificial epitaxial layer using a dry etch.
18. A method according to claim 17 comprising etching the polished semi-sacrificial epitaxial layer using a reactive ion etch.
19. A method of preparing a substrate and epilayer for reducing stacking fault nucleation and reducing forward voltage (V f ) drift in silicon carbide-based bipolar devices, the method comprising:
selectively etching the surface of a silicon carbide substrate from which surface and subsurface damage have been removed to thereby develop etch-generated structures from at least any basal plane dislocations on the substrate that will thereafter tend to either terminate or to propagate as threading dislocations during subsequent epilayer growth on the substrate surface; and thereafter
growing a first conductive epitaxial layer of silicon carbide on the selectively-etched surface.
20. A method according to claim 19 comprising selectively etching the surface with a molten salt.
21. A substrate-preparation method according to claim 20 comprising etching the surface with a molten salt selected from the group consisting of potassium hydroxide, mixtures of potassium hydroxide and sodium hydroxide, and a eutectic mixture of potassium hydroxide and sodium hydroxide.
22. A method according to claim 19 comprising growing a second conductive epilayer above the first conductive epilayer and having the opposite conductivity type from the first conductive epilayer.