Methods of manufacturing group III nitride semiconductor devices with silicon nitride layers

1. A method of fabricating a transistor, the method comprising:

providing a first Group III nitride layer on a substrate in a reactor;

providing a second Group III nitride layer that is undoped or doped with an n-type dopant on the first Group III nitride layer in-situ in the reactor;

providing an insulating layer directly on the second Group III nitride layer in-situ in the reactor;

removing the substrate including the first Group III nitride layer, the second Group III nitride layer and the insulating layer from the reactor;

patterning the insulating layer to form at least a first contact hole that exposes a first contact region of the second Group III nitride layer while leaving a portion of the insulating layer on the second Group III nitride layer; and

providing a first contact on the first contact region of the second Group III nitride layer.

2. The method of claim 1 , wherein the second Group III nitride layer comprises an undoped, n-type gallium nitride based layer of the transistor, and

wherein the method further comprises forming a passivation layer on the insulating layer ex situ after the substrate including the first Group III nitride layer, the second Group III nitride layer and the insulating layer is removed from the reactor.

3. The method of claim 2 , wherein the insulating layer is a silicon nitride layer.

4. The method of claim 3 , wherein the silicon nitride layer is formed at a growth rate of at least about 0.2 microns/hour.

5. The method of claim 4 , wherein an oxygen concentration in the silicon nitride layer is less than about 3×10 18 atoms/cm 3 .

6. The method of claim 4 , wherein the silicon nitride layer has a thickness of at least about 250 Angstroms.

7. The method of claim 4 , wherein the silicon nitride layer has a thickness of at least about 1000 Angstroms.

8. The method of claim 3 , wherein a hydrogen concentration in the silicon nitride layer is less than about 1×10 22 atoms/cm 3 .

9. The method of claim 8 , wherein an oxygen concentration in the silicon nitride layer is less than about 3×10 19 atoms/cm 3 .

10. The method of claim 3 , wherein the silicon nitride layer is formed directly on the second Group III nitride layer, and wherein the surface of the second Group III nitride layer adjoining the silicon nitride layer has a pit density of less than about 0.25 pits per μm 2 .

11. The method of claim 3 , wherein the silicon nitride layer has a BOE etch rate of less than about 10 Angstroms per minute.

12. The method of claim 3 , wherein the silicon nitride layer is grown without a process stop after growth of the second Group III nitride layer.

13. The method of claim 3 , wherein the silicon nitride layer is directly on the second Group III nitride layer, and wherein the surface of the second Group III nitride layer adjoining the silicon nitride layer has a pit density of less than about 0.01 pits per μm 2 .

14. The method of claim 1 , wherein the insulating layer is a boron nitride layer.

15. The method of claim 1 , wherein the transistor comprises a High Electron Mobility Transistor, and wherein the first Group III nitride layer comprises a Group III nitride channel layer, wherein the second Group III nitride layer comprises a Group III nitride barrier layer, and wherein the insulating layer is a silicon nitride layer.

16. The method of claim 15 , wherein the silicon nitride layer is formed using a pure silicon gas source.

17. The method of claim 15 , wherein the sheet resistance of the Group III nitride channel layer following formation of the metal contacts is less than about two times the sheet resistance of the Group III nitride channel layer as grown.

18. The method of claim 15 , wherein the sheet resistance of the Group III nitride channel layer following formation of the metal contacts is less than about 1.1 times the sheet resistance of the Group III nitride channel layer as grown.

19. The method of claim 1 , wherein the second Group III nitride layer comprises an undoped aluminum gallium nitride layer.

20. A method of fabricating a Group III nitride semiconductor device, the method comprising:

providing a Group III nitride semiconductor channel layer on a substrate using a first source material containing a Group III metal and a second source material containing nitrogen;

providing a Group III nitride semiconductor barrier layer doped with silicon on the Group III nitride semiconductor channel layer using the first source material containing the Group III metal, the second source material containing nitrogen and a first silicon gas source; and

providing a silicon nitride layer directly on the Group III nitride semiconductor barrier layer using a second silicon gas source wherein the second silicon gas source has a higher silicon concentration than the first silicon gas source.

21. The method of claim 20 , wherein the Group III nitride semiconductor channel layer, the Group III nitride semiconductor barrier layer and the first silicon nitride layer are formed via MOCVD.

22. The method of claim 20 , wherein:

the Group III nitride semiconductor device comprises a HEMT transistor, and

providing the silicon nitride layer on the Group III nitride semiconductor barrier layer comprises forming the silicon nitride layer on the Group III nitride semiconductor barrier layer via MOCVD in-situ in the reactor.

23. The method of claim 22 , wherein the silicon nitride layer is directly on the Group III nitride semiconductor barrier layer, and wherein the surface of the Group III nitride semiconductor barrier layer adjoining the silicon nitride layer has a pit density of less than about 0.001 pits per μm 2 .

24. The method of claim 20 , wherein providing the silicon nitride layer on the Group III nitride semiconductor barrier layer comprises forming the silicon nitride layer on the Group III nitride semiconductor barrier layer at a growth rate of at least about 0.2 microns/hour.

25. The method of claim 20 , the method further comprising:

removing portions of the silicon nitride layer to expose the Group III nitride semiconductor barrier layer; and then

forming a passivation layer directly on the remaining silicon nitride layer.

26. The method of claim 20 , wherein the hydrogen concentration in the silicon nitride layer is less than about 3×10 21 atoms/cm 3 .

27. The method of claim 26 , wherein the oxygen concentration in the silicon nitride layer is less than about 3×10 19 atoms/cm 3 .

28. The method of claim 20 , wherein the silicon nitride layer has a thickness of at least about 250 Angstroms.

29. The method of claim 20 , wherein the silicon nitride layer has a BOE etch rate of less than about 10 Angstroms per minute.

30. The method of claim 20 , wherein the silicon nitride layer is grown at about the same temperature and the same pressure as the Group III nitride semiconductor barrier layer, and using the same nitrogen source gas.

31. The method of claim 20 , wherein the second silicon source gas is a pure silicon source gas.

32. A method of fabricating a transistor, the method comprising:

providing a first Group III nitride layer on a substrate in a reactor;

providing a second Group III nitride layer that is undoped or doped with an n-type dopant on the first Group III nitride layer in-situ in the reactor;

providing an insulating layer directly on the second Group III nitride layer in-situ in the reactor;

removing the substrate including the first Group III nitride layer, the second Group III nitride layer and the insulating layer from the reactor;

patterning the insulating layer to form at least a first contact hole that exposes a first contact region of the second Group III nitride layer while leaving a portion of the insulating layer on the second Group III nitride layer;

providing a first contact on the first contact region of the second Group III nitride layer; and

forming a passivation layer on the protective layer ex situ after the substrate including the first Group III nitride layer, the second Group III nitride layer and the insulating layer is removed from the reactor,

wherein the first Group III nitride layer comprises a channel layer of the transistor,

wherein the second Group III nitride layer comprises an undoped, n-type gallium nitride based barrier layer of the transistor, and

wherein the insulating layer comprises a protective layer.

33. A method of fabricating a transistor, the method comprising:

forming a first n-type gallium nitride based channel layer on a substrate in a reactor;

forming a second n-type gallium nitride based barrier layer that is doped with silicon on the first n-type gallium nitride based channel layer in-situ in the reactor;

forming a silicon nitride protective layer directly on the second n-type gallium nitride based barrier layer in-situ in the reactor;

removing the substrate including the first n-type gallium nitride based channel layer, the second n-type gallium nitride based barrier layer and the silicon nitride protective layer from the reactor; and then

patterning the silicon nitride protective layer to form at least a first contact hole that exposes a first contact region of the second n-type gallium nitride based barrier layer while leaving a portion of the silicon nitride protective layer on the second n-type gallium nitride based barrier layer; and

providing a first contact on the first contact region of the second n-type gallium nitride based barrier layer.