IP Library Granted Patent US 7,432,142
Granted Patent B2
US 7,432,142 · App. 10/849,617 · Granted Oct 7, 2008

Methods of fabricating nitride-based transistors having regrown ohmic contact regions

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,432,142
App. No.
10/849,617
Granted
Oct 7, 2008
Kind
B2
Abstract

Transistor fabrication includes forming a nitride-based channel layer on a substrate, forming a barrier layer on the nitride-based channel layer, forming a contact recess in the barrier layer to expose a contact region of the nitride-based channel layer, forming a contact layer on the exposed contact region of the nitride-based channel layer, for example, using a low temperature deposition process, forming an ohmic contact on the contact layer and forming a gate contact disposed on the barrier layer adjacent the ohmic contact. A high electron mobility transistor (HEMT) and methods of fabricating a HEMT are also provided. The HEMT includes a nitride-based channel layer on a substrate, a barrier layer on the nitride-based channel layer, a contact recess in the barrier layer that extends into the channel layer, an n-type nitride-based semiconductor material contact region on the nitride-based channel layer in the contact recess, an ohmic contact on the nitride-based contact region and a gate contact disposed on the barrier layer adjacent the ohmic contact. The n-type nitride-based semiconductor material contact region and the nitride-based channel layer include a surface area enlargement structure.

Claims (76)

1. A method of fabricating a transistor, comprising:

forming a nitride-based channel layer on a substrate;

forming a barrier layer on the nitride-based channel layer;

forming a contact recess in the barrier layer to expose a contact region of the nitride-based channel layer;

forming a contact layer on the exposed contact region of the nitride-based channel layer using a low temperature deposition process;

forming an ohmic contact on the contact layer;

forming a gate contact disposed on the barrier layer adjacent the ohmic contact;

forming a first dielectric layer on the barrier layer;

forming a gate recess in the first dielectric layer;

wherein forming a gate contact comprises forming a gate contact in the gate recess; and

wherein forming a contact recess comprises forming an ohmic contact recess in the first dielectric layer and the barrier layer that expose a portion of the nitride-based channel layer.

2. The method of claim 1 , wherein the first dielectric layer comprises a silicon nitride layer.

3. The method of claim 2 , wherein the silicon nitride layer provides a passivation layer for the transistor.

4. A method of fabricating a transistor, comprising:

forming a nitride-based channel layer on a substrate;

forming a barrier layer on the nitride-based channel layer;

forming a contact recess in the barrier layer to expose a contact region of the nitride-based channel layer;

forming a contact layer on the exposed contact region of the nitride-based channel layer using a low temperature deposition process;

forming an ohmic contact on the contact layer;

forming a gate contact disposed on the barrier layer adjacent the ohmic contact;

forming a first dielectric layer on the barrier layer;

wherein forming a gate contact comprises forming a gate contact in the first dielectric layer; and

wherein forming a contact recess comprises forming an ohmic contact recess in the first dielectric layer and the barrier layer that expose a portion of the nitride-based channel layer.

5. A method of fabricating a transistor, comprising:

forming a nitride-based channel layer on a substrate;

forming a barrier layer on the nitride-based channel layer;

forming a contact recess in the baffler layer to expose a contact region of the nitride-based channel layer;

forming a contact layer on the exposed contact region of the nitride-based channel layer using a low temperature deposition process;

forming an ohmic contact on the contact layer; forming a gate contact disposed on the baffler layer adjacent the ohmic contact;

forming holes in the channel layer adjacent the contact regions;

placing n-type nitride-based semiconductor material in the holes; and

wherein forming an ohmic contact on the contact layer comprises forming an ohmic contact on the contact layer and on the n-type nitride-based semiconductor material in the holes.

6. A method of fabricating a transistor, comprising:

forming a nitride-based channel layer on a substrate;

forming a barrier layer on the nitride-based channel layer;

forming a masking layer on the barrier layer;

patterning the masking layer and the barrier layer to provide a contact opening that exposes a portion of the nitride-based channel layer;

forming a contact layer on the exposed portion of the nitride-based channel layer and the masking layer;

selectively removing the masking layer and a portion of the contact layer on the masking layer to provide a nitride-based contact region;

forming an ohmic contact on the nitride-based contact region; and

forming a gate contact disposed on the barrier layer adjacent the ohmic contact.

7. The method of claim 6 , further comprising:

forming a first dielectric layer on the barrier layer;

forming a recess in the first dielectric layer;

wherein forming a gate contact comprises forming a gate contact in the recess;

wherein forming a masking layer on the barrier layer comprises forming a masking layer on the first dielectric layer; and

wherein patterning the masking layer and the barrier layer to provide a contact opening that exposes a portion of the nitride-based channel layer comprises patterning the masking layer, the first dielectric layer and the barrier layer to provide a contact opening that exposes a portion of the nitride-based channel layer.

8. The method of claim 6 , wherein the first dielectric layer comprises a silicon nitride layer.

9. The method of claim 8 , wherein the silicon nitride layer provides a passivation layer for the transistor.

10. The method of claim 6 , wherein the masking layer comprises a dielectric layer.

11. The method of claim 10 , wherein the dielectric layer comprises a silicon oxide layer.

12. The method of claim 6 , wherein the masking layer comprises a photoresist and/or e-beam resist masking layer.

13. The method of claim 6 , wherein forming an ohmic contact comprises forming an ohmic contact without annealing the ohmic contact.

14. The method of claim 6 , wherein forming an ohmic contact comprises:

patterning a metal layer on the nitride-based contact region; and

annealing the patterned metal layer at a temperature of less than about 850 C.

15. The method of claim 6 , wherein forming a nitride based contact layer on the exposed portion of the nitride-based channel layer and the masking layer comprises forming a nitride based contact layer by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), plasma enchanced chemical vapor deposition (PECVD), sputtering and/or hydride vapor phase epitaxy (HVPE).

16. The method of claim 6 , wherein forming a nitride based contact layer on the exposed portion of the nitride-based channel layer and the masking layer comprises forming a nitride based contact layer on the exposed portions of the nitride-based channel layer and the masking layer to a thickness sufficient to provide a sheet resistivity of less than a sheet resistivity of a two-dimensional electron gas region formed at an interface between the channel layer and the baffler layer.

17. The method of claim 6 , wherein forming a nitride based contact layer comprises forming n-type an InGaN, GaN, AlGaN, InAlGaN, InAlN and/or InN layer.

18. The method of claim 17 , wherein the InGaN, GaN, AlGaN, InAlGaN, InAlN and/or InN layer is doped with Si, Ge and/or O during formation.

19. The method of claim 6 , wherein the nitride based contact layer comprises an n-type degenerate semiconductor material other than GaN and AlGaN.

20. The method of claim 19 , wherein the nitride based contact layer comprises a non-nitride Group III-V semiconductor material, a Group IV semiconductor material and/or a group II-VI semiconductor material.

21. The method of claim 6 , further comprising forming sidewalls of the channel layer to provide an increased surface area interface between the nitride based channel layer and the nitride based contact layer in comparison to a planar interface.

22. The method of claim 21 , wherein forming an ohmic contact comprises forming an ohmic contact on the nitride-based contact region that extends onto a portion of the channel layer.

23. The method of claim 21 , wherein forming an ohmic contact comprises forming an ohmic contact on the nitride-based contact region that terminates before the sidewall of the channel layer.

24. The method of claim 6 , further comprising:

forming holes in the channel layer adjacent the nitride-based contact region;

wherein forming a nitride based contact layer further comprises placing a nitride-based semiconductor material in the holes; and

wherein forming an ohmic contact on the nitride-based contact region comprises forming an ohmic contact on the nitride-based contact region and on the nitride-based semiconductor material in the holes.

25. The method of claim 6 , wherein the contact opening comprises a first contact opening, the nitride-based contact region comprises a first nitride-based contact region and the ohmic contact comprises a first ohmic contact, the method further comprising:

patterning the masking layer and the barrier layer to provide a second contact opening that exposes a portion of the nitride-based channel layer;

forming a nitride based contact layer on the portion of the nitride-based channel layer exposed by the second contact opening;

wherein selectively removing the masking layer comprises selectively removing the masking layer and a portion of the nitride based contact layer on the masking layer to provide the first nitride-based contact region and a second nitride-based contact region;

forming a second ohmic contact on the second nitride-based contact region; and

wherein forming a gate contact comprises forming a gate contact disposed on the barrier layer between the first and second ohmic contacts.

26. The method of claim 6 , further comprising a contact recess that exposes a portion of the barrier layer and wherein forming a nitride based contact layer comprises forming a contact layer that extends onto the exposed portion of the barrier layer.

Assignments (3)
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL AT REEL/FRAME NO. 64185/0755 Recorded Sep 30, 2025
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WOLFSPEED, INC.
Reel/Frame 072989/0001 →
SECURITY INTEREST Recorded Jun 30, 2023
From: WOLFSPEED, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
Reel/Frame 064185/0755 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2004
From: SAXLER, ADAM WILLIAM; SMITH, RICHARD PETER
To: CREE, INC.
Reel/Frame 015369/0001 →