Heap and stack layout for multithreaded processes in a processing system
View Patent ↗A method and system in accordance with the present invention comprises a thread stack/thread heap combination, wherein the thread heap is for thread local memory usage and wherein the thread stack and thread heap grow in opposite directions. In the present invention the thread specific heap is allocated next to the thread's stack and grows in the opposite direction from that of the stack. This improvement allows the current space management of thread stacks, which spread out the memory placement of multiple stacks to avoid collision, to also be used for the heaps without additional overhead or complexity. It also allows the existing growth scheme of adding memory pages to the process for the stack to be used again because the growth is simply in the opposite direction. Thread specific heaps eliminate the need for expensive synchronization when allocating from a shared heap in a multiprocessor environment.
1. A method for reducing contention in a multithreaded processor; the method comprising the steps of
(a) providing at least two thread stack/thread heap combinations in an address space on the processor, wherein each thread heap is for thread local memory usage and wherein each thread stack and thread heap combination grows in opposite directions; and
(b) providing a dead zone between the at least two thread stack/thread heap combinations, wherein data can not be written to, read from and executed from the dead zone.
2. The method of claim 1 wherein the providing step (a) further comprises the steps of:
(a1) providing a base address for each thread stack;
(a2) creating an initialization for each thread heap from the base address; and
(a3) assigning memory regions in the address space to each thread stack and thread heap combination.
3. The method of claim 2 , further comprising the step of (a4) allowing the assigned memory regions of each thread stack and thread heap combination to grow in opposite directions as needed.
4. A computer readable medium containing program instructions for reducing contention in a multithreaded processor; the program including instructions for:
(a) providing at least two thread stack/thread heap combinations in an address space on the processor, wherein each thread heap is for thread local memory usage and wherein each thread stack and thread heap combination grows in opposite directions; and
(b) providing a dead zone between the at least two thread stack/thread heap combinations, wherein data can not be written to, read from and executed from the dead zone.
5. The computer readable medium of claim 4 wherein the program instructions (a); further comprise the steps of:
(a1) providing a base address for each thread stack;
(a2) creating an initialization for each thread heap from the base address; and
(a3) assigning memory regions in the address space to each thread stack and thread heap combination.
6. The computer readable medium of claim 5 , wherein the instructions further comprise, instructions for (a4) allowing the assigned memory regions of each thread stack and thread heap combination to grow in opposite directions as needed.
7. A system for reducing contention in a multithreaded processor; the system comprising:
means for providing at least two thread stack/thread heap combinations in an address space on the processor, wherein each thread heap is for thread local memory usage and wherein each thread stack and thread heap combination grows in opposite directions,
means for providing a dead zone between the two thread stack/thread heap combinations, wherein data can not be written to, read from and executed from the dead zone.
8. The system of claim 7 wherein the means for providing at least two thread stack/thread heap combinations further comprises:
means for providing a base address for each thread stack;
means for creating an initialization for each thread heap from the base address; and
means for assigning memory regions in the address space to each thread stack and thread heap combination.
9. The system of claim 8 which includes means for allowing the assigned memory regions of each thread stack and thread heap combination to grow in opposite directions as needed.