A memory controller converts controller output signals output from a controller int memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
1. A common memory controller for controlling different types of memory chips which are connected to a common bus, comprising:
a first interface portion for receiving a control output signal to access said memory chips from a controller, and outputting a control input signal to the controller;
a conversion control portion for converting said control output signal into a memory input signal in response to a specification of each of said memory chips to which the memory controller is connected, and converting a memory output signal output from the memory chips into the control input signal receivable to said controller;
a second interface portion for outputting the memory input signal and receiving the memory output signal; and
a plurality of terminals coupled to the second interface portion for connecting the second interface portion to the different types of memory chips via said common bus.
2. The common memory controller according to claim 1 , wherein the different types of memory chips include a synchronous DRAM or a synchronous SRAM.
3. The common memory controller according to claim 1 , further comprising
a memory unit for storing the specification of the memory chip, and wherein the memory unit is programmable.
4. The common memory controller according to claim 1 , wherein the specification of memory chip includes a memory type, a command sequence, an address sequence or latency information.
5. The common memory controller according to claim 1 , wherein the second interface portion controls an output timing of the memory input signal in response to the specification of memory chip.
6. The common memory controller according to claim 1 , wherein the memory input signal includes an address, a command, and data.
7. The common memory controller according to claim 6 , wherein the memory input signal further includes a chip select signal.
8. The common memory controller according to claim 6 , wherein the memory input signal further includes a direct memory access control signal.
9. The common memory controller according to claim 1 , wherein the number of the plurality of terminals is larger than that of the terminals of each of the memory chips to which the memory controller is connected.
10. The common memory controller according to claim 1 , wherein the plurality of terminals include control terminals, address terminals, data terminals, and a clock terminal.
11. A multi chip package comprising:
a system LSI chip including a common memory controller for controlling different types of memory chips which are connected to a common bus; and
memory chips coupled to the system LSI chip, and controlled by the common memory controller,
the common memory controller including:
a first interface portion for receiving a control output signal to access said memory chips from a controller of the LSI chip, and outputting a control input signal to the controller;
a conversion control portion for converting said control output signal into a memory input signal in response to a specification of each of the memory chips, and converting a memory output signal from the memory chips into the control input signal receivable to said controller;
a second interface portion for outputting the memory input signal and receiving the memory output signal; and
a plurality of terminals coupled to the second interface portion, for connecting the second interface portion to the different types of memory chips via said common bus.
12. The common memory controller according to claim 1 , further comprising
an arbiter circuit for arbitrating an order to access said memory chips when access requests for said memory chips overlap with each other.