Multi-rate, multi-port, gigabit Serdes transceiver
View Patent ↗A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port Serdes transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports. The ring structure of the bus provides efficient communication between the logic core and the various data ports.
1. A transceiver, comprising:
multiple parallel ports;
multiple serial ports;
a bus connecting said multiple parallel ports and said multiple serial ports on a common substrate with said multiple parallel ports and said multiple serial ports; and
a packet bit error rate tester (BERT) connected to said bus, said packet BERT able to determine bit error rates of at least one of said multiple parallel ports and said multiple serial ports.
2. The transceiver of claim 1 , wherein said bus is configured to have a ring shape.
3. The transceiver of claim 1 , wherein said bus is configured to have a ring shape around a logic core.
4. The transceiver of claim 1 , wherein said bus is a parallel bus.
5. The transceiver of claim 4 , wherein each of said serial ports include a serial-to-parallel converter, a parallel port of said serial-to-parallel converter connected to said parallel bus.
6. The transceiver of claim 1 , further comprising at least one custom logic block connected to said bus.
7. A transceiver, comprising:
multiple parallel ports;
multiple serial ports; and
a bus connecting said multiple parallel ports and said multiple serial ports on a common substrate with said multiple parallel ports and said multiple serial ports;
wherein said multiple parallel ports include two parallel ports and said multiple serial ports includes four serial ports.
8. A transceiver, comprising:
multiple parallel ports;
multiple serial ports; and
a bus connecting said multiple parallel ports and said multiple serial ports on a common substrate with said multiple parallel ports and said multiple serial ports;
wherein said multiple parallel ports are XGMII parallel ports.
9. A transceiver, comprising:
multiple parallel ports;
multiple serial ports; and
a bus connecting said multiple parallel ports and said multiple serial ports on a common substrate with said multiple parallel ports and said multiple serial ports;
wherein said multiple serial ports are XAUI serial ports.
10. A transceiver, comprising:
multiple parallel ports;
multiple serial ports; and
a bus connecting said multiple parallel ports and said multiple serial ports on a common substrate with said multiple parallel ports and said multiple serial ports;
wherein said serial ports convert between a XAUI serial protocol and a XGMII parallel protocol using a XGXS conversion protocol.
11. A transceiver, comprising:
multiple parallel ports;
multiple serial ports; and
a parallel bus connecting said multiple parallel ports and said multiple serial ports on a common substrate with said multiple parallel ports and said multiple serial ports;
wherein said parallel bus includes multiple transmission lines having a common path length.
12. The transceiver of claim 11 , wherein data clock rates of said multiple serial ports and said multiple parallel ports are programmable.
13. The transceiver of claim 11 , wherein two of said multiple serial ports are enabled.
14. The transceiver of claim 13 , wherein at least one of said multiple serial ports is disabled.
15. The transceiver of claim 11 , wherein at least one of said multiple parallel ports is enabled.
16. The transceiver of claim 15 , wherein at least one of said multiple parallel ports is disabled.
17. The transceiver of claim 11 , further comprising a configuration block that enables and disables said multiple parallel ports and said multiple serial ports to configure said transceiver.
18. A transceiver, comprising:
multiple parallel ports;
multiple serial ports;
a bus connecting said multiple parallel ports and said multiple serial ports on a common substrate with said multiple parallel ports and said multiple serial ports; and
at least one management pad, said management pad able to determine data protocols and electricals for said transceiver.
19. The transceiver of claim 18 , wherein said management pad is responsive to two or more protocols.
20. The transceiver of claim 19 , wherein said two or more protocols include an IEEE Std 802.3 clause 22 management standard and an IEEE Std 802.3 clause 45 management standard.
21. The transceiver of claim 18 , wherein said management pad is responsive to a data protocol of a first type of standard, and an electrical protocol of a second type of standard.
22. The transceiver of claim 21 , wherein said first type of standard is one of an IEEE Std 802.3 clause 45 standard and an IEEE Std 802.3 clause 22 standard, and said second type of standard is the other of said IEEE Std 802.3 clause 45 standard and said IEEE Std 802.3 clause 22 standard.