Method for fabricating a semiconductor structure
View Patent ↗The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS 1 , GS 2 , GS 3 , GS 4 ) on a semiconductor substrate ( 10 ), having the following steps: application of the gate stacks (GS 1 , GS 2 , GS 3 , GS 4 ) to a gate dielectric ( 11 ) above the semiconductor substrate ( 10 ); formation of a sidewall oxide ( 17 ) on sidewalls of the gate stacks (GS 1 , GS 2 , GS 3 , GS 4 ); application and patterning of a mask ( 12 ) on the semiconductor structure; and implantation of a contact doping ( 13 ) in a self-aligned manner with respect to the sidewall oxide ( 17 ) of the gate stacks (GS 1 , GS 2 ) in regions not covered by the mask ( 12 ).
1. Method for fabricating a semiconductor structure having a plurality of gate stacks on a semiconductor substrate, having the following steps:
(a) applying the gate stacks to a gate dielectric above the semiconductor substrate;
(b) forming a sidewall oxide on sidewalls of the gate stacks;
(c) applying and patterning of mask on the semiconductor structure;
(d) implanting a contact doping in a self-aligned manner with respect to the sidewall oxide of the gate stacks in regions not covered by the mask; and
(e) after implanting the contact doping, reducing the sidewall oxide in its lateral extent in regions not covered by the mask for resulting in a thinned sidewall oxide.
2. Method according to claim 1 , wherein the reduction of the extent of the lateral sidewall oxide for resulting in a thinned side wall oxide is followed by a further implantation of different doping.
3. Method according to claim 2 , wherein the further doping is a p-type doping having a low concentration, preferably with a dopant concentration that is at least a power of ten lower than the contact doping concentration.
4. Method according to claim 2 , wherein the further doping is a bit line halo doping implanted from a predetermined direction at a predetermined angle α, preferably in the range of between about 0° and 30° inclusive.
5. Method according to claim 1 , wherein the contact doping is implanted at a predetermined angle of α=0°.
6. Method according to claim 1 , wherein the contact doping is an n-type doping having a high concentration, for example having an implantation dose of about 10 14 to 3·10 15 /cm 2 , preferably with arsenic.
7. Method according to claim 1 , wherein a removal of the mask is followed by an implantation of a, preferably identical, dopant having a lower dopant concentration than that of the contact doping.
8. Method according to claim 1 , wherein the gate stacks are applied approximately equidistantly with respect to one another, a storage capacitor being arranged alternately below every third or first adjacent gate in the semiconductor substrate in a cross-sectional plane.
9. Method according to claim 1 , wherein the method is used for fabricating logic transistors.
10. Method according to claim 1 , wherein the method is used for fabricating selection transistors, preferably of a DRAM.
11. Method according to claim 1 , wherein the gate stacks are fabricated with a length of less than 200 nm.
12. Method according to claim 1 , wherein the gate stacks are provided parallel and in strip-type fashion on the semiconductor substrate.
13. Method according to claim 1 , wherein the gate stacks have a lower first layer made of polysilicon and an overlying second layer made of a metal silicide or a metal.
14. Method according to claim 1 , wherein the gate stacks are created by carrying out an application and patterning of the first layer, the overlying second layer and a third layer arranged thereon on the gate dielectric.
15. Method according to claim 14 , wherein the third layer has silicon nitride or oxide.