Shared volatile and non-volatile memory
View Patent ↗The invention includes an apparatus and a method that provides a memory back-up system. The memory back-up system includes a first memory cell, and a non-volatile memory cell that is interfaced to the first memory cell. Control circuitry allows data to be written to either the first memory cell or the non-volatile memory cell, and provides transfer of the data from either the first memory cell or the non-volatile memory cell, to the other of either the first memory cell or the non-volatile memory cell. The memory back-up system can also include a plurality of first memory cells, and a plurality of non-volatile memory cells that are interfaced to the first memory cells. Control circuitry allows data to be written to either the first memory cells or the non-volatile memory cells, and that provides transfer of the data from either the first memory cells or the non-volatile memory cells, to the other of either the first memory cells or the non-volatile memory cells.
1. A memory back-up system comprising:
a volatile memory cell;
a non-volatile memory cell, the non-volatile memory cell being integrated with the volatile memory cell, the non-volatile memory cell being interfaced with the volatile memory cell;
a single word line WL connected to the integrated volatile memory cell and the non-volatile memory cell, the single word line WL allowing data to be simultaneously written to the volatile memory cell and the non-volatile memory cell.
2. The memory back-up system of claim 1 , wherein the volatile memory cell is a DRAM memory cell and the non-volatile memory cell is an MRAM memory cell.
3. The memory back-up system of claim 1 , further comprising a second control line which in combination with the single word line WL provides selection of the volatile memory cell.
4. The memory back-up system of claim 1 , further comprising a third control line which in combination with the single word line WL provides selection of the non-volatile memory cell.
5. The memory back-up system of claim 1 , further comprising a
an array volatile memory cells;
an array of non-volatile memory cells, each non-volatile memory cell interfaced with a corresponding volatile memory cell;
a plurality of word lines WL, each single word line WL connected to a corresponding plurality of volatile memory cells and the non-volatile memory cells, the word line WL allowing data to be simultaneously written to the corresponding plurality of volatile memory cells and the non-volatile memory cells.
6. A memory back-up system comprising:
a plurality of first memory cells;
a plurality of non-volatile memory cells that are interfaced to the first memory cells;
control circuitry that allows data to be written to one of the first memory cells and the non-volatile memory cells, and that provides transfer of the data from one of the first memory cells and the non-volatile memory cells to the other one of the first memory cells and the non-volatile memory cells.
7. The memory back-up system of claim 6 , wherein the control circuitry further includes allowing data to be read from one of the first memory cell and the non-volatile memory cell.
8. A computing device comprising:
a controller;
a memory unit interfaced with the controller, the memory unit comprising;
an array volatile memory cells;
an array of non-volatile memory cells, each non-volatile memory cell integrated and interfaced with a corresponding volatile memory cell; and
a plurality of word lines WL, each word line WL connected to a corresponding plurality of the integrated volatile memory cells and the non-volatile memory cells, the word line WL allowing data to be simultaneously written to the corresponding plurality of volatile memory cells and the non-volatile memory cells.
9. An image storing device comprising:
means for receiving an image;
a memory unit for storing the image, the memory unit comprising;
an array volatile memory cells;
an array of non-volatile memory cells, each non-volatile memory cell integrated and interfaced with a corresponding volatile memory cell; and
a plurality of word lines WL, each word line WL connected to a corresponding plurality of the integrated volatile memory cells and the non-volatile memory cells, the word line WL allowing data to be simultaneously written to the corresponding plurality of volatile memory cells and the non-volatile memory cells.
10. The memory back-up system of claim 9 , further comprising a plurality word lines, wherein a single word line WL is connected to both a first memory cell and a non-volatile memory cell.
11. The memory back-up system of claim 10 , wherein the single word line WL is connected to a DRAM controlling transistor gate of the DRAM memory cell and a to a MRAM controlling transistor gate of the MRAM memory cell.
12. A memory back-up system comprising:
a volatile memory cell;
a non-volatile memory cell that is interfaced with the volatile memory cell;
a single word line WL connected to the volatile memory cell and the non-volatile memory cell, the single word line WL allowing data to be simultaneously written to the volatile memory cell and the non-volatile memory cell; wherein
the volatile memory cell is a DRAM memory cell and the non-volatile memory cell is an MRAM memory cell.