IP Library Assignment 019733/0030
Patent Assignment
Reel/Frame 019733/0030

Assignment of Assignor's Interest

Recorded: 2007-08-22 Pages: 33
Assignor
Assignee
SAMSUNG ELECTRONICS CO., LTD.
416 MAETAN-DONG, YEONGTONG-GU, SUWON-SI, GYEONGGI-DO, KOREA, REPUBLIC OF
Covered Properties (50)
Information Storage Device Including Heating Elements for Magnetic Memory Elements
Patent: 6,603,678 →
Application: 09/758,757 →
Publication: US 2002/0089874
Cladded Read Conductor for a Pinned-on-the-Fly Soft Reference Layer
Patent: 6,538,920 →
Application: 09/825,093 →
Publication: US 2002/0186582
Multi-Function Serial I/O Circuit
Patent: 6,587,384 →
Application: 09/839,012 →
Publication: US 2002/0154536
Resistive Cross Point Memory with on-Chip Sense Amplifier Calibration Method and Apparatus
Patent: 6,504,779 →
Application: 09/855,118 →
Publication: US 2002/0167838
Resistive Cross Point Array of Short-Tolerant Memory Cells
Patent: 6,633,497 →
Application: 09/887,314 →
Publication: US 2002/0196647
Image Capture and Storage Device
Patent: 7,027,092 →
Application: 09/953,988 →
Publication: US 2003/0052983
Magneto-Resistive Device Having Soft Reference Layer
Patent: 6,576,969 →
Application: 09/963,171 →
Publication: US 2003/0058684
Read Methods for Magneto-Resistive Device Having Soft Reference Layer
Patent: 6,538,917 →
Application: 09/963,851 →
Publication: US 2003/0058685
Magneto-Resistive Device Including Soft Reference Layer Having Embedded Conductors
Patent: 6,504,221 →
Application: 09/963,932 →
Method for Modifying Switching Field Characteristics of Magnetic Tunnel Junctions
Patent: 6,649,423 →
Application: 09/971,347 →
Publication: US 2003/0067802
Test Array and Method for Testing Memory Arrays
Patent: 6,639,859 →
Application: 09/983,697 →
Publication: US 2003/0081477
Write Current Compensation for Temperature Variations in Memory Arrays
Patent: 6,608,790 →
Application: 09/998,216 →
Publication: US 2003/0103401
Nonlinear Digital Differential Amplifier Offset Calibration
Patent: 6,586,989 →
Application: 10/005,456 →
Publication: US 2003/0085758
Magnetoresistive Random Access Memory (Mram) with on-Chip Automatic Determination of Optimized Write Current Method and Apparatus
Patent: 6,606,262 →
Application: 10/044,724 →
Publication: US 2003/0128578
Low Temperature Systems for Use with Magnetoresistive Circuit Components
Patent: 6,597,597 →
Application: 10/053,385 →
Publication: US 2003/0090931
Memory Systems and Methods of Making the Same
Patent: 6,594,171 →
Application: 10/093,020 →
Multi-Port Scan Chain Register Apparatus and Method
Patent: 6,848,067 →
Application: 10/107,939 →
Publication: US 2003/0188240
Magnetic Memory Device
Patent: 6,657,890 →
Application: 10/176,715 →
Publication: US 2003/0235074
Multi-Bit Magnetic Memory Device
Patent: 6,577,529 →
Application: 10/235,011 →
Mram Parallel Conductor Orientation for Improved Write Performance
Patent: 6,809,958 →
Application: 10/243,469 →
Publication: US 2004/0052104
Write Current Compensation for Temperature Variations in Memory Arrays
Patent: 6,577,549 →
Application: 10/254,559 →
Publication: US 2003/0103402
Magneto-Resistive Device Including Clad Conductor
Patent: 6,693,825 →
Application: 10/349,685 →
Magneto-Resistive Device Having Soft Reference Layer
Patent: 6,891,746 →
Application: 10/351,013 →
Publication: US 2003/0137868
Magnetic Memory Cell
Patent: 6,747,335 →
Application: 10/355,787 →
Memory Device and Method of Use
Patent: 6,982,901 →
Application: 10/355,788 →
Low Temperature Systems for Use with Magnetoresistive Circuit Components
Patent: 6,628,543 →
Application: 10/361,097 →
Publication: US 2003/0112658
Magnetoresistive Random Access Memory (Mram) with on-Chip Automatic Determination of Optimized Write Current Method and Apparatus
Patent: 6,865,104 →
Application: 10/459,635 →
Publication: US 2003/0210596
Method for Modifying Switching Field Characteristics of Magnetic Tunnel Junctions
Patent: 6,828,610 →
Application: 10/626,447 →
Publication: US 2004/0129928
Method and Article for Concentrating Fields at Sense Layers
Patent: 6,791,872 →
Application: 10/652,446 →
Publication: US 2004/0042302
A Method of Forming a Shared Global Word Line Mram Structure
Patent: 6,927,092 →
Application: 10/656,758 →
Publication: US 2004/0047213
System and Method for Determining the Logic State of a Memory Cell in a Magnetic Tunnel Junction Memory Device
Patent: 6,999,334 →
Application: 10/660,831 →
Publication: US 2005/0099855
Method and Article for Concentrating Fields at Sense Layers
Patent: 6,791,857 →
Application: 10/668,442 →
Publication: US 2004/0057303
Systems and Methods for Communicating with Memory Blocks
Patent: 6,842,390 →
Application: 10/675,191 →
Publication: US 2004/0066691
Magnetic Memory Element Having Controlled Nucleation Site in Data Layer
Patent: 6,905,888 →
Application: 10/676,414 →
Publication: US 2004/0062125
Memory Device Array Having a Pair of Magnetic Bits Sharing a Common Conductor Line
Patent: 6,879,508 →
Application: 10/692,617 →
Publication: US 2004/0090809
Triple Sample Sensing for Magnetic Random Access Memory (Mram) with Series Diodes
Patent: 6,873,544 →
Application: 10/696,826 →
Publication: US 2004/0090841
Magneto Resistive Storage Device Having a Magnetic Field Sink Layer
Patent: 6,919,594 →
Application: 10/696,991 →
Publication: US 2004/0090842
Multi-Bit Magnetic Memory Cells
Patent: 6,862,212 →
Application: 10/697,172 →
Publication: US 2004/0090844
Magnetic Memory Device Having Soft Reference Layer
Patent: 6,891,212 →
Application: 10/697,191 →
Publication: US 2004/0089889
Shared Volatile and Non-Volatile Memory
Patent: 6,894,918 →
Application: 10/697,367 →
Publication: US 2004/0202022
Memory Device Capable of Calibration and Calibration Methods Therefor
Patent: 6,791,874 →
Application: 10/753,298 →
Publication: US 2004/0141370
Magnetic Memory Cell Having an Annular Data Layer and a Soft Reference Layer
Patent: 6,903,403 →
Application: 10/902,925 →
Publication: US 2005/0014320
Asymmetric Patterned Magnetic Memory
Patent: 6,921,954 →
Application: 10/932,693 →
Publication: US 2005/0073016
Magnetic Memory Storage Device
Patent: 6,977,839 →
Application: 11/064,883 →
Publication: US 2005/0139883
Method of Making a Magnetic Tunnel Junction Device
Patent: 6,998,662 →
Application: 11/080,092 →
Publication: US 2005/0156215
Magnetic Memory Structure Using Heater Lines to Assist in Writing Operations
Patent: 7,196,957 →
Application: 11/105,054 →
Publication: US 2005/0185453
Multi-Bit Mram Device with Switching Nucleation Sites
Patent: 7,078,244 →
Application: 11/112,815 →
Publication: US 2005/0195649
Data Storage Device and Method of Forming the Same
Patent: 7,031,185 →
Application: 11/171,694 →
Publication: US 2005/0237845
Method and System for Data Communication on a Chip
Patent: 7,142,448 →
Application: 11/211,986 →
Publication: US 2005/0281078
Memory Device and Method of Use
Patent: 7,139,191 →
Application: 11/268,059 →
Related Assignments (5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Aug 6, 2001
From: SHARMA, MANISH; TAN, LUNG T
To: HEWLETT-PACKARD COMPANY
Reel/Frame 012060/0461 →
Assignment of Assignor's Interest Sep 4, 2001
From: PERNER, FREDERICK A.
To: HEWLETT-PACKARD COMPANY
Reel/Frame 012137/0779 →
Assignment of Assignor's Interest Sep 17, 2001
From: ALTREE, MICAHEL
To: HEWLETT-PACKARD COMPANY
Reel/Frame 012182/0342 →
Assignment of Assignor's Interest Sep 24, 2001
From: PERNER, FREDERICK A
To: HEWLETT-PACKARD COMPANY
Reel/Frame 012184/0901 →
Assignment of Assignor's Interest Dec 31, 2001
From: NICKEL, JANICE H.
To: HEWLETT-PACKARD COMPANY
Reel/Frame 012417/0333 →