Method and system for data communication on a chip
View Patent ↗Methods and apparatuses are disclosed for communicating data on a chip. In one embodiment, the method includes: reading the data value of a memory element utilizing conductors that are electrically coupled to the memory element, and communicating the value read from the memory element to other locations on chip using write conductors that are magnetically coupled to the memory element.
1. A memory, comprising:
a memory element;
a control circuit;
a write conductor that is magnetically coupled to the memory element and electrically coupled to the control circuit; and
wherein said write conductor is capable of communicating non-write data.
2. The memory of claim 1 , wherein said non-write data includes a data value stored in the memory element that is read utilizing the write conductor that is magnetically coupled to the memory element.
3. The memory of claim 1 , further comprising a first buffer, a second buffer, and a latch, wherein the write conductor is electrically coupled to the control circuit using said first buffer, and wherein said second buffer and said latch are electrically coupled to the write conductor.
4. The memory of claim 3 , further comprising a latch electrically coupled to the write conductor and the second buffer, wherein said latch couples data between said write conductor and said second buffer.
5. The memory of claim 4 , wherein the buffers comprise tri-state buffers.
6. The memory of claim 5 , wherein said first buffer is enabled by the control circuit and said second buffer is disabled by the control circuit and the write conductor conveys non-write data.
7. The memory of claim 5 , wherein said first buffer is enabled by the control circuit and said second buffer is enabled by the control circuit and the write conductor conducts a variable amount of current.
8. The memory of claim 7 , wherein the current in the write conductor causes a desired magnetic field in the memory element.
9. The memory of claim 8 , wherein the magnetic field may be adjusted by varying the amount and direction of current in the write conductor.
10. A means for storing data in memory, comprising:
loading means, for loading a first buffer that is electrically coupled to a write conductor with a data value;
enabling means, for enabling the first buffer such that the data value occupies the write conductor;
retaining means, for retaining the data value from write conductor;
loading means, for loading a second buffer that is electrically coupled to the write conductor; and
enabling means, for enabling the second buffer such that the write conductor conducts a variable amount of current.
11. The means for storing data of claim 10 , wherein the write conductor is magnetically coupled to a memory and a current flowing in the write conductor causes a magnetic field in the memory.
12. The means for storing data of claim 10 , wherein the amount and direction of current in the write conductor is capable of being adjusted using the buffers.
13. A computer system, comprising:
a processor;
a bridge logic device coupled to said processor;
a system memory coupled to said processor, wherein said memory includes:
at least one memory element;
a control circuit;
a write conductor that is magnetically coupled to the memory element and electrically coupled to the control circuit; and
wherein said write conductor is capable of communicating non-write data.
14. The memory of claim 13 , wherein said non-write data includes a data value stored in the memory element that is read utilizing the write conductor that is magnetically coupled to the memory element.
15. The memory of claim 13 , further comprising a first buffer, a second buffer, and a latch, wherein the write conductor is electrically coupled to the control circuit using said first buffer, and wherein said second buffer and said latch are electrically coupled to the write conductor.
16. The memory of claim 15 , further comprising a latch electrically coupled to the write conductor and the second buffer, wherein said latch couples data between said write conductor and said second buffer.
17. The memory of claim 15 , wherein the buffers comprise tri-state buffers.
18. The memory of claim 17 , wherein said first buffer is enabled by the control circuit and said second buffer is disabled by the control circuit and the write conductor conveys non-write data.
19. The memory of claim 17 , wherein said first buffer is enabled by the control circuit and said second buffer is enabled by the control circuit and the write conductor conducts a variable amount of current.
20. A memory circuit, comprising:
a first buffer loaded with non-write data and electrically coupled to a write conductor;
a second buffer electrically coupled to the write conductor;
wherein the write conductor is magnetically coupled to at least one magnetic memory element;
wherein the second buffer is disabled and the first buffer is enabled, thereby allowing the non-write data in the first buffer to be conveyed to other areas of the memory circuit.
21. The memory circuit of claim 20 , further comprising a latch circuit coupled to the second buffer, wherein the latch circuit retains write data conveyed on the write conductor.
22. The memory circuit of claim 21 , wherein the write data in the latch circuit is conveyed to the second buffer when the second buffer is enabled.
23. The memory circuit of claim 20 , wherein electrical current is capable of flowing in either direction in the write conductor thereby altering a digital state of the memory element.
24. The memory circuit of claim 20 , further comprising a control circuit capable of arbitrating control of the write conductor between write and non-write states.