DRAM cell structure capable of high integration and fabrication method thereof

1. A DRAM cell structure capable of high integration, comprising:

a trench-type capacitor formed in a lower region of a trench, the trench being made vertically and cylindrically in a silicon substrate; and

a transistor formed vertically and cylindrically over the trench-type capacitor, the transistor being connected to the capacitor, said transistor including,

a storage node contact plug stacked over the trench-type capacitor;

a source formed by being diffused into a p-well region of the silicon substrate of the trench sidewall;

a poly connector stacked over the storage node contact plug, the poly connector connecting the plug and the source;

a nitride film or an oxide film stacked over the poly connector to thereby isolate a gate electrode and the poly connector;

a gate electrode stacked over the film, the gate electrode being connected to a word-line;

a gate isolation film deposited on the silicon substrate of the trench sidewall adjacent to the gate electrode;

a drain formed through an implanting process between gate electrodes, the drain being connected to a bit-line.

2. The DRAM cell structure of claim 1 , wherein the trench-type capacitor includes:

a plate electrode formed by being diffused into the silicon substrate of a lower sidewall of the trench;

an insulator formed by being thinly deposited on the lower sidewall of the trench, the insulator being adjacent to the plate electrode;

a storage node electrode formed on the insulator, corresponding to the plate electrode.

3. The DRAM cell structure of claim 2 , wherein the insulator is a capacitor insulation film formed on the lower sidewall of the trench, the capacitor insulation film being capable of charge accumulation.

4. The DRAM cell structure of claim 2 , wherein an oxide film is stacked in the trench in which the storage node electrode is formed.

5. The DRAM cell structure of claim 1 , wherein the storage node contact plug is formed through a process of depositing an oxide film on the trench sidewall over the storage node electrode and stacking a contact conductor in the trench on which the oxide film is formed to thereby connect to the storage node electrode.

6. The DRAM cell structure of claim 5 , wherein the storage node contact plug is formed in the buried n-well region and an n-well region of the silicon substrate in the trench.

7. The DRAM cell structure of claim 5 , wherein the oxide film is formed by thermal oxidation to a depth of about several hundred angstroms or more.

8. The DRAM cell structure of claim 1 , wherein the poly connector is formed by stacking polysilicon doped with n-type impurity over the storage node contact plug in the trench to thereby be connected to the storage node contact plug.

9. The DRAM cell structure of claim 1 , wherein the source is formed by diffusing n-type impurity of poly connector material into an adjacent silicon substrate of the trench sidewall through an annealing process.

10. The DRAM cell structure of claim 1 , wherein the gate electrode is formed by stacking polysilicon in the trench over the nitride film.

11. The DRAM cell structure of claim 10 , wherein the gate electrode protrudes on the silicon substrate to a height of about several hundred angstroms or more.

12. The DRAM cell structure of claim 11 , wherein the gate electrode is connected to a word-line of a DRAM cell via a word-line contact hole, the word-line contact hole being formed over the gate electrode by etching.

13. The DRAM cell structure of claim 12 , wherein a word-line contact plug is formed by depositing poly electrode or tungsten in the word-line contact hole to thereby connect the gate electrode and the word-line.

14. The DRAM cell structure of claim 1 , wherein the drain is connected to the bit-line of the DRAM cell via a bit-line contact hole, the bit-line contact hole being formed over the drain by etching.

15. The DRAM cell structure of claim 14 , wherein a bit-line contact plug is formed by depositing poly, poly electrode or tungsten in the bit-line contact hole, to thereby connect the bit-line and the drain.

16. The DRAM cell structure of claim 14 , wherein a device isolation film is formed between the drain region and the p-well region to thereby isolate transistor devices in adjacent trenches.

17. The DRAM cell structure of claim 16 , wherein the device isolation film is of SOI structure for a device unit, the device isolation film being formed by stacking an oxide film on a device isolation hole, the device isolation hole being formed in the drain region and the p-well region by etching.

18. The DRAM cell structure of claim 16 , wherein the bit-line connects two transistor devices in adjacent trenches.

19. A DRAM cell structure capable of high integration, comprising:

a trench-type capacitor formed in a lower region of trench, the trench being made vertically and cylindrically in a silicon substrate and including,

a plate electrode formed in a buried n-well region in the silicon substrate by diffusing n-type impurity of an LPTEOS layer into the silicon substrate of a lower sidewall of the trench;

an insulator formed by being deposited on the lower sidewall of the trench, the insulator being adjacent to the plate electrode;

a storage node electrode formed on the insulator, corresponding to the plate electrode; and

a transistor formed vertically and cylindrically over the trench-type capacitor, the transistor being connected to the capacitor.

20. A DRAM cell structure of claim 19 , wherein said transistor includes:

a storage node contact plug stacked over the trench-type capacitor;

a source formed in a p-well region of the silicon substrate of the trench sidewall;

a poly connector stacked over the storage node contact plug, the poly connector connecting the plug and the source;

nitride film or an oxide film stacked over the poly connector to thereby isolate the poly connector;

a gate electrode stacked over the film, the gate electrode being connected to a word-line;

a gate isolation film deposited on the silicon substrate of the trench sidewall adjacent to the gate electrode; and

a drain formed between gate electrodes, the drain being connected to a bit-line.