IP Library Granted Patent US 7,268,763
Granted Patent B2
US 7,268,763 · App. 10/701,856 · Granted Sep 11, 2007

Method for driving display and drive circuit for display

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Quick Facts
Patent No.
US 7,268,763
App. No.
10/701,856
Granted
Sep 11, 2007
Kind
B2
Abstract

A drive circuit of a display that decreases the number of gates in a selection circuit to reduce chip area. The drive circuit includes a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage. A selection circuit receives a selection signal and selects one of the divisional voltages. The selection circuit includes a plurality of first switch circuits selectively activated in response to the selection signal to select one of the divisional voltages. Each of the first switch circuits is provided with a logic switch function and has an ON resistance when activated. An activated one of the first switch circuits generates the pixel voltage by further dividing the selected one of the divisional voltages.

Claims (34)

1. A method for generating pixel voltage to drive a display, the method comprising:

generating a plurality of divisional voltages by dividing a predetermined reference voltage;

selecting one of the divisional voltages by selectively activating at least one of a plurality of first switch circuits with a selection signal, wherein each of the first switch circuits has an ON resistance when activated;

activating at least one voltage dividing switch circuit connected to the plurality of first switch circuits, wherein the at least one voltage dividing switch circuit has an ON resistance when activated; and

generating the pixel voltage by further dividing the selected one of the divisional voltages with the ON resistance of the activated one of the first switch circuits and the ON resistance of the at least one voltage dividing circuit.

2. The method according to claim 1 , wherein said generating the pixel voltage includes:

generating a plurality of pixel voltages by dividing the selected one of the divisional voltages; and

selecting one of the plurality of pixel voltages with the selection signal.

3. A drive circuit for a display, the drive circuit comprising:

a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage; and

a selection circuit connected to the first voltage dividing circuit to receive a selection signal and select one of the divisional voltages, the selection circuit including:

a plurality of first switch circuits that are selectively activated in response to the selection signal to select one of the divisional voltages, with each of the first switch circuits being provided with a logic switch function and having an ON resistance when activated, and

at least one voltage dividing switch circuit connected to the plurality of first switch circuits, wherein the at least one voltage dividing switch circuit has an ON resistance when activated, an activated one of the first switch circuits and the at least one voltage dividing switch circuit generating a pixel voltage for supply to the display by further dividing the selected one of the divisional voltages with the ON resistance of the activated one of the first switch circuits and the ON resistance of the at least one voltage dividing circuit.

4. The drive circuit according to claim 3 , further comprising:

an operational amplifier for supplying the pixel voltage to the display;

wherein the activated one of the first switch circuits and the at least one voltage dividing switch circuit configure a second voltage dividing circuit for generating a plurality of pixel voltages, and the selection circuit includes a plurality of second switch circuits connected to the at least one voltage dividing switch circuit to selectively supply one of the pixel voltages to the operational amplifier.

5. The drive circuit according to claim 3 , wherein the voltage dividing circuit includes a plurality of series-connected ladder resistors for generating the plurality of divisional voltages from the predetermined reference voltage, and the activated one of the first switch circuits is connected in parallel to one of the ladder resistors.

6. The drive circuit according to claim 5 , wherein one of the first switch circuits and the at least one voltage dividing switch circuit are activated and connected in series to one another.

7. The drive circuit according to claim 3 , wherein the first switch circuits are configured so that their ON resistances all have substantially the same value.

8. The drive circuit according to claim 3 , wherein the selection circuit is one of a plurality of selection circuits, the first voltage dividing circuit is connected to the selection circuits, the divisional voltages are supplied to each of the plurality of selection circuits, and each of the first switch circuit in each of the plurality of selection circuits has an impedance that is adjusted in accordance with the distance from the first voltage dividing circuit.

9. The drive circuit according to claim 3 , wherein the first voltage dividing circuit divides the predetermined reference voltage to generate a plurality of further divisional voltages, and the selection circuit includes a selection unit connected to the first voltage dividing circuit to select one of the further divisional voltages in accordance with the selection signal and generate the pixel voltage.

10. The drive circuit according to claim 3 , wherein:

the first voltage dividing circuit includes a positive voltage dividing circuit for generating a plurality of positive divisional voltages and a negative voltage dividing circuit for generating a plurality of negative divisional voltages;

the selection circuit includes a first selection circuit for selecting one of the positive divisional voltages and a second selection circuit for selecting one of the negative divisional voltages;

the first switch circuits in the first selection circuit are p-channel MOS transistors connected to the positive voltage dividing circuit; and

the second switch circuits in the first selection circuit are n-channel MOS transistors connected to the negative voltage dividing circuit.

11. A method for generating a predetermined voltage with a digital signal, the method comprising:

generating a plurality of divisional voltages by dividing a predetermined reference voltage;

selecting one of the divisional voltages by selectively activating at least one of a plurality of first switch circuits with the digital signal, wherein each of the first switch circuits has an ON resistance when activated;

activating at least one voltage dividing switch circuit connected to the plurality of first switch circuits, wherein the at least one voltage dividing switch circuit has an ON resistance when activated; and

generating the predetermined voltage by further dividing the selected one of the divisional voltages with the ON resistance of the activated one of the first switch circuits and the ON resistance of the at least one voltage dividing circuit.

12. The method according to claim 11 , wherein said generating the predetermined voltage includes:

generating a plurality of predetermined voltages by dividing the selected one of the divisional voltages; and

selecting one of the plurality of predetermined voltages with the digital signal.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0337 →
CHANGE OF NAME Recorded Jul 19, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024706/0890 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2003
From: FUKUDA, HIDETO; UDO, SHINYA; KUMAGAI, MASAO; KUDO, OSAMU
To: FUJITSU LIMITED
Reel/Frame 014674/0638 →