IP Library Granted Patent US 6,888,181
Granted Patent B1
US 6,888,181 · App. 10/708,694 · Granted May 3, 2005

Triple gate device having strained-silicon channel

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Quick Facts
Patent No.
US 6,888,181
App. No.
10/708,694
Granted
May 3, 2005
Kind
B1
Abstract

A three-dimensional Triple-Gate (Tri-gate) device having a three-sided strained silicon channel and superior drive current is provided. The Tri-gate device includes a composite fin structure consisting of a silicon germanium core and a three-sided strained silicon epitaxy layer grown from surface of said silicon germanium core. A gate strip wraps a channel portion of the composite fin structure. Two distal end portions of the composite fin structure not covered by the gate strip constitute source/drain regions of the Tri-gate device. A high quality gate insulating layer is interposed between the composite fin structure and the gate strip.

Claims (16)

1. A three dimensional Triple Gate (Tri-gate) device comprising:

a composite fin structure consisting of a silicon germanium core and a strained silicon epitaxy layer grown from surface of said silicon germanium core;

a gate strip wrapping a portion of said composite fin structure, wherein portions of said composite fin structure not covered by said gate strip constitute source/drain regions of said Tri-gate device; and

a gate insulating layer interposed between said composite fin structure and said gate strip.

2. The Tri-gate device of claim 1 wherein said composite fin structure has a substantially flat top surface and vertical sidewalls.

3. The Tri-gate device of claim 2 wherein said composite fin structure has a width of said flat top surface that is approximately equal to its height.

4. The Tri-gate device of claim 1 wherein said strained silicon epitaxy layer has a thickness of about 50˜300 angstroms.

5. The Tri-gate device of claim 1 wherein said gate strip is made of polysilicon or metal gate.

6. A Tri-gate device comprising:

a composite fin structure consisting of a semiconductor core and a strained epitaxy layer grown from surface of said semiconductor core, said semiconductor core having a first lattice constant that miss-matches a second lattice constant of said strained epitaxy layer;

a gate strip wrapping a portion of said composite fin structure, wherein portions of said composite fin structure not covered by said gate strip constitute source/drain regions of said Tri-gate device; and

a gate insulating layer interposed between said composite fin structure and said gate strip.

7. The Tri-gate device of claim 6 wherein said semiconductor core consists of silicon germanium.

8. The tri-gate device of claim 6 wherein said strained epitaxy layer is a strained silicon epitaxy layer.

9. The tri-gate device of claim 8 wherein said strained silicon epitaxy layer has thickness of about 50˜300 angstroms.

10. The Tri-gate device of claim 6 wherein said gate strip is made of polysilicon or metal gate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2004
From: LIAO, WEN-SHIANG; SHIAU, WEI-TSUN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 014430/0719 →