Wet etching process
The present invention illustrates a bulk silicon etching technique that yields straight sidewalls, through wafer structures in very short times using standard silicon wet etching techniques. The method of the present invention employs selective porous silicon formation and dissolution to create high aspect ratio structures with straight sidewalls for through wafer MEMS processing.
1. A bulk silicon etching method comprising the following steps in the order named:
(a) providing a silicon wafer;
(b) diffusing the wafer with dopant, whereby the diffusion creates a PN-junction at a predetermined PN-junction depth throughout the surface of the wafer;
(c) providing a mask;
(d) positioning the mask in overlying relation to the surface of the wafer;
(e) patterning a layer of oxide on the surface of the wafer, whereby the pattern of the oxide layer is defined by the mask;
(f) etching the wafer to create recesses in the wafer in the areas that are not patterned with the oxide layer, whereby the etching step is sufficient to etch away the wafer to a depth below the PN-junction depth created by the diffusion step, thereby creating recessed areas having sidewalls, the sidewalls characterized by the presence of the PN-junction above the PN-junction depth and the absence of the PN-junction below the PN-junction depth;
(g) hydrofluoric acid etching the wafer to form porous silicon thereon, whereby the porous silicon is formed in the sidewalls of the recessed areas characterized by the absence of the PN-junction; and
(h) subjecting the wafer to wet etching resulting in dissolution of the porous silicon.
2. The method of claim 1 , wherein the silicon wafer is an N-type silicon wafer.
3. The method of claim 1 , wherein the dopant is a P-type dopant.
4. The method of claim 1 , wherein the silicon wafer is a P-type silicon wafer.
5. The method of claim 1 , wherein the dopant is an N-type dopant.
6. The method of claim 1 , wherein the step (e) of patterning a layer of oxide on the surface of the wafer further comprises sputtering the oxide layer.
7. The method of claim 1 , wherein the step (f) of etching the wafer further comprises etching the wafer with potassium hydroxide.
8. The method of claim 7 , further comprising etching the wafer with potassium hydroxide for about ten minutes.
9. The method of claim 1 , wherein the step (h) of subjecting the wafer surface to wet etching, further comprises subjecting the wafer surface to potassium hydroxide.
10. The method of claim 1 , wherein the step (h) of subjecting the wafer surface to wet etching, further comprises subjecting the wafer surface to tetramethyl ammonium hydroxide.
11. The method of claim 9 , wherein the wafer surface is subjected to potassium hydroxide for about thirty seconds.
12. The method of claim 10 , wherein the wafer surface is subjected to tetramethyl ammonium hydroxide for about thirty seconds.