FinFET with low gate capacitance and low extrinsic resistance
View Patent ↗A FinFET device and a method of lowering a gate capacitance and extrinsic resistance in a field effect transistor, wherein the method comprises forming an isolation layer comprising a BOX layer over a substrate, configuring source/drain regions above the isolation layer, forming a fin structure over the isolation layer, configuring a first gate electrode adjacent to the fin structure, disposing a gate insulator between the first gate electrode and the fin structure, positioning a second gate electrode transverse to the first gate electrode, and depositing a third gate electrode on the fin structure, the first gate electrode, and the second gate electrode, wherein the isolation layer is formed beneath the insulator, the first gate electrode, and the fin structure. The method further comprises sandwiching the second gate electrode with a dielectric material. The fin structure is formed by depositing an oxide layer over a silicon layer.
1. A field effect transistor (FET) comprising:
a fin structure;
conducting spacers contacting said fin structure, wherein an upper surface of said conducting spacers is substantially planar with an upper surface of said fin structure;
an insulator contacting said spacers, wherein said insulator is structurally isolated from said fin structure; and
a gate layer positioned on top of and contacting said fin structure, said spacers, and said insulator.
2. The FET of claim 1 , further comprising:
a substrate; and
an isolation layer positioned over said substrate,
wherein said isolation layer is positioned under said insulator, said spacers, and said fin structure.
3. The FET of claim 2 , farther comprising source/drain regions above said isolation layer.
4. The FET of claim 1 , wherein said fin structure comprises an oxide layer over a silicon layer.
5. The FET of claim 1 , further comprising an oxide layer contacting said fin structure.
6. The FET of claim 4 , further comprising a second oxide layer over said oxide layer, wherein said second oxide layer is planar to said gate layer.
7. The FET of claim 1 , wherein said spacers and said gate layer comprise the same material.
8. The FET of claim 7 , wherein said material comprises polysilicon.
9. The FET of claim 1 , further comprising a gate insulator positioned between said fin structure and said spacers.
10. The FET of claim 1 , further comprising a second insulator contacting said insulator.
11. A field effect transistor (FET) device comprising:
a fin structure;
a first gate electrode contacting said fin, structure;
a gate insulator positioned between said first gate electrode and said fin structure;
a second gate electrode positioned transverse to said first gate electrode; and
a third gate electrode positioned on top of and contacting said fin structure, said first gate electrode, and said second gate electrode.
12. The device of claim 11 , further comprising:
a substrate; and
an isolation layer positioned over said substrate,
wherein said isolation layer is positioned beneath said gate insulator, said first gate electrode, and said fin structure.
13. The device of claim 12 , wherein said isolation layer is isolated from said second gate electrode.
14. The device of claim 12 , further comprising source/drain regions above said isolation layer.
15. The device of claim 11 , further comprising a dielectric material sandwiching said second gate electrode.
16. The device of claim 11 , wherein said fin structure comprises an oxide layer over a silicon layer.
17. The device of claim 11 , further comprising an oxide layer contacting said fin structure.
18. The device of claim 16 , further comprising a second oxide layer over said oxide layer, wherein said second oxide layer is planar to said third gate electrode.
19. The device of claim 11 , wherein said first gate electrode and said third gate electrode comprise the same material.
20. The device of claim 19 , wherein said material comprises polysilicon.
21. A method of lowering a gate capacitance and extrinsic resistance in a field effect transistor (FET), said method comprising:
forming a fin structure;
configuring a first gate electrode contacting said fin structure;
disposing a gate insulator between said first gate electrode and said fin structure;
positioning a second gate electrode transverse to said first gate electrode; and
depositing a third gate electrode on top of and contacting said fin structure, said first gate electrode, and said second gate electrode.
22. The method of claim 21 , further comprising forming an isolation layer over a substrate, wherein said isolation layer comprises a buried oxide (BOX) layer, and wherein said isolation layer is positioned beneath said gate insulator, said first gate electrode, and said fin structure.
23. The method of claim 22 , further comprising configuring source/drain regions above said isolation layer.
24. The method of claim 21 , further comprising sandwiching said second gate electrode with a dielectric material.
25. The method of claim 21 , wherein said fin structure is formed by depositing an oxide layer over a silicon layer.
26. The method of claim 21 , further comprising forming an oxide layer contacting said fin structure.
27. The method of claim 25 , further comprising forming a second oxide layer over said oxide layer, wherein said second oxide layer is planar to said third gate electrode.
28. The method of claim 21 , further comprising using the same material to form said first gate electrode and said third gate electrode.
29. The method of claim 28 , wherein said material comprises polysilicon.