Method of fabricating micro-chips
View Patent ↗A method of fabricating micro-chips, including: (a) providing a substrate; (b) forming a first single-crystal layer on a top surface of the substrate; (c) forming a second single-crystal layer on a top surface of the first single-crystal layer; (d) forming integrated circuits in the second single-crystal layer; (e) forming a set of intersecting trenches in the second-single crystal layer to form single-crystal islands, each single-crystal island containing one or more of the integrated circuits, the first single-crystal layer exposed in a bottom of the trench; and (f) removing the first single-crystal layer in order to separate the single-crystal islands from the substrate.
1. A method, comprising:
(a) providing a substrate;
(b) forming a first single-crystal layer on a top surface of said substrate;
(c) forming a second single-crystal layer on a top surface of said first single-crystal layer;
(d) forming one or more devices in said second single-crystal layer;
(e) forming a trench in said second-single crystal layer, said trench surrounding said one or more devices, to form a single-crystal island containing said one or more devices in a region of said second single-crystal layer, said first single-crystal layer exposed in a bottom of said trench; and
(f) removing said first single-crystal layer in order to separate said single-crystal island from said substrate.
2. The method of claim 1 , wherein step (f) includes selectively removing said first single-crystal layer with respect to said second-single crystal layer.
3. The method of claim 1 , wherein said substrate comprises silicon.
4. The method of claim 1 , wherein said first single-crystal layer comprises Si x Ge y , Si x C y or Si x As y .
5. The method of claim 1 , wherein said second single-crystal layer comprises silicon.
6. The method of claim 1 , further including:
(g) after step (f) repeating steps (a) through (f) one or more times.
7. The method of claim 1 , further including:
(g) after step (f) mechanical-chemical-polishing said substrate to expose a new top surface of said substrate; and
(h) after step (g) repeating steps (a) through (g) one or more times.
8. The method of claim 1 , further including:
between steps (e) and (f), forming a spacer on peripheral sidewalls of said single crystal island.
9. The method of claim 1 , wherein said one or more devices are independently selected from the group consisting of NFETS, PFETs, bipolar transistors, resistors and capacitors.
10. The method of claim 1 , wherein step (d) further includes interconnecting said one or more devices to form an integrated circuit in said second-single crystal layer.
11. The method of claim 10 , wherein said integrated circuit is a radio frequency identification circuit.
12. The method of claim 1 , wherein said trench comprises one or more intersecting trenches.
13. A method, comprising:
(a) providing a single-crystal substrate;
(b) forming a buried single-crystal layer in said substrate;
(c) forming one or more devices in said a layer of said single-crystal substrate above said buried single-crystal layer;
(d) forming a trench surrounding said one or more devices in a region of said layer of said single-crystal substrate above said buried single-crystal layer to form a single-crystal island containing said one or more devices, said buried single-crystal layer exposed in a bottom of said trench; and
(e) removing said buried single-crystal layer in order to separate said single-crystal island from said substrate.
14. The method of claim 13 , wherein step (b) includes performing an ion implantation of Ge or As or C followed by performing a heat treatment.
15. The method of claim 13 , wherein said substrate comprises silicon.
16. The method of claim 13 , wherein said first single-crystal layer comprises Si x Ge y , Si x C y or Si x As y and said second single-crystal layer comprises silicon.
17. The method of claim 13 , wherein said one or more devices are independently selected from the group consisting of NFETS, PFETs, bipolar transistors, resistors and capacitors.
18. The method of claim 13 , wherein step (d) further includes interconnecting said one or more devices to form an integrated circuit in said second-single crystal layer.
19. The method of claim 18 , wherein said integrated circuit is a radio frequency identification circuit.
20. The method of claim 13 , wherein said trench comprises one or more intersecting trenches.
21. A method, comprising:
(a) providing a substrate;
(b) forming a first single-crystal layer on a top surface of said substrate;
(c) forming a second single-crystal layer on a top surface of said first single-crystal layer;
(d) forming one or more devices in said second single-crystal layer;
(e) forming a trench in said second-single crystal layer to form a single-crystal island containing said one or more devices, said first single-crystal layer exposed in a bottom of said trench; and
(f) removing said first single-crystal layer in order to separate said single-crystal island from said substrate.