IP Library › Assignment 026664/0866
Patent Assignment
Reel/Frame 026664/0866

ASSIGNMENT OF ASSIGNOR'S INTEREST

Recorded: 2011-07-12 Received: 2011-07-12 Pages: 42
Assignor
Assignee
GOOGLE INC.
1600 AMPHITHEATRE PARKWAY, MOUNTAIN VIEW, CA, 94043 US, UNITED STATES
Covered Applications (100)
CABLE RESTRAINT
App. No. 11/539,046
→
CONTROLLED SELF-ADJUSTING PROCESS FOR REDUCING SELECTED DIMENSIONS OF ELECTRONIC PRODUCTS
App. No. 11/532,365
→
AUTONOMIC DATA ASSURANCE APPLIED TO COMPLEX DATA-INTENSIVE SOFTWARE PROCESSES BY MEANS OF PATTERN RECOGNITION
App. No. 11/464,365
→
AN OPEN-ENDED SPIN TOOL
App. No. 11/459,670
→
ACTIVE IMPENDANCE CURRENT-SHARE METHOD
App. No. 11/423,331
→
APPARATUS FOR HYSTERESIS BASED PROCESS COMPENSATION FOR CMOS RECEIVER CIRCUITS
App. No. 11/279,658
→
ELECTRONIC PACKAGE STRUCTURES USING LAND GRID ARRAY INTERPOSERS FOR MODULE-TO-BOARD INTERCONNECTION
App. No. 11/386,343
→
A REAL-TIME ADAPTIVE SRAM ARRAY FOR HIGH SEU IMMUNITY
App. No. 11/308,215
→
DRIVER FOR MULTI-VOLTAGE ISLAND/CORE ARCHITECTURE
App. No. 11/276,169
→
AUTOMATED TOOL RECIPE VERIFICATION AND CORRECTION
App. No. 11/307,293
→
FAST DATA STREAM DECODING USING APRIORI INFORMATION
App. No. 11/342,728
→
METHOD AND STRUCTURE FOR LOSSY COMPRESSION OF CONTINUOUS DATA WITH EXTENSIBLE MOTIFS
App. No. 11/333,232
→
PROGRAMMABLE REFERENCE VOLTAGE GENERATOR
App. No. 11/333,613
→
CONNECTOR DRAWER
App. No. 11/329,632
→
JITTER MEASUREMENTS FOR REPETITIVE CLOCK SIGNALS
App. No. 11/327,818
→
DYNAMICALLY DETERMINING YIELD EXPECTATION
App. No. 11/275,176
→
METHOD AND APPARATUS FOR IMPLEMENTING SUBTHRESHOLD LEAKAGE REDUCTION IN LSDL
App. No. 11/304,142
→
REDUCING DAMAGE TO ULK DIELECTRIC DURING CROSS-LINKED POLYMER REMOVAL
App. No. 11/164,290
→
METHOD AND MECHANICAL TAMPER-EVIDENT CASE FASTENER
App. No. 11/246,823
→
METHOD AND APPARATUS FOR REDUCING NOISE IN A DYNAMIC MANNER
App. No. 11/163,015
→
STRUCTURE AND METHOD FOR PROVIDING GATE LEAKAGE ISOLATION LOCALLY WITHIN ANALOG CIRCUITS
App. No. 11/163,013
→
ROM LOAD BALANCING FOR BIT LINES
App. No. 11/232,767
→
METHOD AND SYSTEM FOR EMBEDDING WIRE MODEL OBJECTS IN A CIRCUIT SCHEMATIC DESIGN
App. No. 11/232,745
→
METHOD AND SYSTEM FOR MODELING WIRING ROUTING IN A CIRCUIT DESIGN
App. No. 11/232,747
→
IMPLEMENTING A HIGH RESOLUTION MONOTONIC SYSTEM CLOCK
App. No. 11/232,763
→
METHOD AND APPARATUS FOR GENERATING SPREAD SPECTRUM CLOCK SIGNALS HAVING HARMONIC EMISSION SUPPRESSIONS
App. No. 11/232,749
→
SIDEWALL IMAGE TRANSFER (SIT) TECHNOLOGIES
App. No. 11/162,662
→
APPARATUS AND METHOD FOR VERIFYING GLITCH-FREE OPERATION OF A MULTIPLEXER
App. No. 11/227,026
→
BITLINE VARIABLE METHODS AND CIRCUITS FOR EVALUATING STATIC MEMORY CELL DYNAMIC STABILITY
App. No. 11/225,571
→
EASY RELEASE SERVER COOLING FAN WITH INTEGRATED SPRING AND METHOD FOR USING SAME
App. No. 11/223,875
→
SECURE ELECTRONIC VOTING DEVICE
App. No. 11/162,306
→
RING OSCILLATOR STRUCTURE AND METHOD OF SEPARATING RANDOM AND SYSTEMATIC TOLERANCE VALUES
App. No. 11/162,197
→
DELIMITER LOOKUP USING PROCESSOR PERMUTATION INSTRUCTION
App. No. 11/215,694
→
METHOD AND APPARATUS FOR PRESETTING AN AMPLIFIER
App. No. 11/162,098
→
PROGRAMMABLE DRIVER DELAY
App. No. 11/211,955
→
METHOD AND APPARATUS FOR IMPLEMENTING COMMON MODE CABLE NOISE SUPPRESSION FOR MEDIUM RANGE FREQUENCIES
App. No. 11/212,008
→
REDUCED CROSS-TALK SIGNALING CIRCUIT AND METHOD
App. No. 11/209,549
→
DIFFERENTIAL AMPLIFIER OFFSET VOLTAGE MINIMIZATION INDEPENDENTLY FROM COMMON MODE VOLTAGE ADJUSTMENT
App. No. 11/203,860
→
METHODS AND APPARATUS FOR RING OSCILLATOR BASED MOSFET GATE CAPACITANCE MEASUREMENTS
App. No. 11/197,918
→
METHODS AND APPARATUS FOR MEMORY CALIBRATION
App. No. 11/191,418
→
A METHOD AND APPARATUS FOR CORRECTING GRAVITATIONAL SAG IN PHOTOMASKS USED IN THE PRODUCTION OF ELECTRONIC DEVICES
App. No. 11/161,215
→
METHOD AND APPARATUS FOR IMPLEMENTING FAULT TOLERANT PHASE LOCKED LOOP (PLL)
App. No. 11/186,595
→
METHODS AND APPARATUS FOR ACCESSING MEMORY
App. No. 11/186,606
→
GLITCH PROTECT VALID CELL AND METHOD FOR MAINTAINING A DESIRED STATE VALUE
App. No. 11/184,346
→
MULTI-LEVEL MAPPING OF TAPE ERROR RECOVERIES
App. No. 11/183,540
→
METHOD AND SYSTEM FOR FINDING EVOLVING REGIONS IN GRAPHS WITHOUT PERSISTENT NODE IDENTITY
App. No. 11/180,445
→
CLEARANCE HOLE SIZE ADJUSTMENT FOR IMPEDANCE CONTROL IN MULTILAYER ELECTRONIC PACKAGING AND PRINTED CIRCUIT BOARDS
App. No. 11/160,785
→
METHOD AND APPARATUS FOR MONITORING INTEGRATED CIRCUIT TEMPERATURE THROUGH DETERMINISTIC PATH DELAYS
App. No. 11/160,601
→
APPARATUS AND METHOD FOR IMPLEMENTING AN INTEGRATED CIRCUIT IP CORE LIBRARY ARCHITECTURE
App. No. 11/160,609
→
SYSTEM AND METHOD FOR EXAMINING HIGH-FREQUENCY CLOCK-MASKING SIGNAL PATTERNS AT FULL SPEED
App. No. 11/168,722
→
COMPLIANT THERMAL INTERFACE STRUCTURE WITH VAPOR CHAMBER
App. No. 11/151,831
→
METHOD AND APPARATUS FOR COMPLETELY COVERING A WAFER WITH A PASSIVATING MATERIAL
App. No. 11/160,154
→
DIGITAL POWER MONITOR AND ADAPTIVE SELF-TUNING POWER MANAGEMENT
App. No. 11/148,090
→
PROGRAMMING AND DETERMINING STATE OF ELECTRICAL FUSE USING FIELD EFFECT TRANSISTOR HAVING MULTIPLE CONDUCTION STATES
App. No. 11/160,056
→
DESIGN VERIFICATION
App. No. 10/908,786
→
APPARATUS AND METHOD FOR EFFICIENT TRANSMISSION OF UNALIGNED DATA
App. No. 11/138,837
→
AN AUTOMATED AND ELECTRICALLY ROBUST METHOD FOR PLACING POWER GATING SWITCHES IN VOLTAGE ISLANDS
App. No. 10/908,619
→
CHIP PACKAGE HAVING CHIP EXTENSION AND METHOD
App. No. 10/908,615
→
CLOCK SCALING TO OPTIMIZE PLL CLOCK GENERATION ACCURACY
App. No. 11/131,621
→
APPARATUS EMPLOYING PREDICTIVE FAILURE ANALYSIS BASED ON IN-CIRCUIT FET ON-RESISTANCE CHARACTERISTICS
App. No. 11/124,940
→
COOLING APPARATUS, COOLED ELECTRONIC MODULE AND METHODS OF FABRICATION THEREOF EMPLOYING AN INTEGRATED COOLANT INLET AND OUTLET MANIFOLD
App. No. 11/124,513
→
COOLING APPARATUS, COOLED ELECTRONIC MODULE AND METHODS OF FABRICATION THEREOF EMPLOYING AN INTEGRATED MANIFOLD AND A PLURALITY OF THERMALLY CONDUCTIVE FINS
App. No. 11/124,064
→
METHOD AND APPARATUS FOR ENCODING BINARY DATA AS A ZERO TERMINATED STRING
App. No. 11/112,776
→
CACHE MEMORY, PROCESSING UNIT, DATA PROCESSING SYSTEM AND METHOD FOR ASSUMING A SELECTED INVALID COHERENCY STATE BASED UPON A REQUEST SOURCE
App. No. 11/109,085
→
PROTECTIVE COVER FOR DIMM CIRCUIT CARD
App. No. 11/106,008
→
METHOD FOR PRESERVING CONSTRAINTS DURING SEQUENTIAL REPARAMETERIZATION
App. No. 11/105,611
→
NON-DESTRUCTIVE IN-SITU ELEMENTAL PROFILING
App. No. 10/907,591
→
SYSTEM AND METHOD FOR MANAGING A CABLE IN A SERVER SYSTEM
App. No. 11/101,272
→
SYSTEMS, METHODS, AND COMPUTER READABLE MEDIUM FOR ANALYZING MEMORY
App. No. 10/907,541
→
OPTICAL TRIGGER FOR PICA TECHNIQUE
App. No. 11/098,850
→
PACKAGING INTEGRATED CIRCUITS FOR ACCELERATED DETECTION OF TRANSIENT PARTICLE INDUCED SOFT ERROR RATES
App. No. 11/098,343
→
METHOD AND APPARATUS OF OPTIMIZING THE IO COLLAR OF A PERIPHERAL IMAGE
App. No. 10/907,499
→
OSCILLATOR ARRAY WITH ROW AND COLUMN CONTROL
App. No. 11/095,895
→
METHOD AND APPARATUS FOR CONTROLLING TRANSITION RATES ON ADJACENT INTERCONNECTS
App. No. 11/094,710
→
CIRCUITS AND METHODS FOR PROVIDING LOW VOLTAGE, HIGH PERFORMANCE REGISTER FILES
App. No. 11/089,941
→
METHOD AND SYSTEM FOR SHREDDING DATA WITHIN A DATA STORAGE SUBSYSTEM
App. No. 11/086,871
→
SYSTEM AND METHOD FOR ENGINE-CONTROLLED CASE SPLITTING WITHIN A MULTIPLE-ENGINE BASED VERIFICATION FRAMEWORK
App. No. 11/082,699
→
SYSTEM AND METHOD FOR OPTIMALLY CONFIGURING SOFTWARE SYSTEMS FOR A NUMA PLATFORM
App. No. 11/077,579
→
METHODS FOR METAL PLATING OF GATE CONDUCTORS AND SEMICONDUCTORS FORMED THEREBY
App. No. 10/906,881
→
ELECTRICAL WIRING DESIGN FOR MODULE REMOVAL AND REPLACEMENT FROM ORGANIC BOARD
App. No. 10/906,816
→
LOGIC CIRCUITS UTILIZING GATED DIODE SENSING
App. No. 11/067,825
→
INTERRUPT MECHANISM ON AN IO ADAPTER THAT SUPPORTS VIRTUALIZATION
App. No. 11/065,951
→
METHOD AND SYSTEM FOR CONTROLLING FORWARDING OR TERMINATING OF A REQUEST AT A BUS INTERFACE BASED ON BUFFER ABVAILABILITY
App. No. 11/064,570
→
METHODS AND APPARATUS FOR USING MEMORY
App. No. 11/064,741
→
PIPELINE BIT HANDLING CIRCUIT AND METHOD FOR A BUS BRIDGE
App. No. 11/064,744
→
METHOD AND SYSTEM FOR FORMAL UNIDIRECTIONAL BUS VERIFICATION USING SYNTHESIZING CONSTRAINED DRIVERS
App. No. 11/065,601
→
WIREBOND CRACK SENSOR FOR LOW-K DIE
App. No. 10/906,507
→
METHOD AND CIRCUIT USING BOUNDARY SCAN CELLS FOR DESIGN LIBRARY ANALYSIS
App. No. 10/906,481
→
A METHOD OF SWITCHING VOLTAGE ISLANDS IN INTEGRATED CIRCUITS WHEN A GRID VOLTAGE AT A REFERENCE LOCATION IS WITHIN A SPECIFIED RANGE
App. No. 10/906,476
→
APPARATUS FOR PERFORMING STUCK FAULT TESTINGS WITHIN AN INTEGRATED CIRCUIT
App. No. 10/906,448
→
Structure for improved diode ideality
App. No. 10/906,366
→
METHOD AND APPARATUS FOR LOCATING AND TESTING A CHIP
App. No. 10/906,306
→
CACHE MEMORY DIRECT INTERVENTION
App. No. 11/056,673
→
METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR SHARING DATA IN A CACHE AMONG THREADS IN AN SMT PROCESSOR
App. No. 11/055,820
→
ECLIPZ WIRETEST FOR DIFFERENTIAL CLOCK/OSCILLATOR SIGNALS
App. No. 11/055,829
→
METHOD AND APPARATUS FOR SPECIFYING MULTIPLE VOLTAGE DOMAINS AND VALIDATING PHYSICAL IMPLEMENTATION AND INTERCONNECTIONS IN A PROCESSOR CHIP
App. No. 11/055,863
→
CONTENT ADDRESSABLE MEMORY INCLUDING A DUAL MODE CYCLE BOUNDARY LATCH
App. No. 11/055,830
→
FENCING OFF INSTRUCTION BUFFER UNTIL RE-CIRCULATION OF REJECTED PRECEDING AND BRANCH INSTRUCTIONS TO AVOID MISPREDICT FLUSH
App. No. 11/056,512
→
METHOD AND APPARATUS FOR DYNAMIC MODIFICATION OF MICROPROCESSOR INSTRUCTION GROUP AT DISPATCH
App. No. 11/055,831
→
CLOCK DUTY CYCLE BASED ACCESS TIMER COMBINED WITH STANDARD STAGE CLOCKED OUTPUT REGISTER
App. No. 11/057,318
→