Method and apparatus for implementing fault tolerant phase locked loop (PLL)

1. Apparatus for implementing a fault tolerant phase locked loop (PLL) circuit comprising:

a divide by N circuit providing an output feedback frequency signal; said divide by N circuit including a plurality of sub-divide by N functions;

said divide by N circuit including compare and reload logic coupled to each said sub-divide by N function;

each of said plurality of sub-divide by N functions including a counter circuitry and an N register storing a factor for dividing a received frequency signal;

said compare and reload logic responsive to identifying a failed counter event, synchronizing said counter circuitry of said plurality of sub-divide by N functions;

a voter circuit coupled to said plurality of sub-divide by N functions; each of said sub-divide by N function providing a feedback frequency signal applied to a voter circuit; and

said voter circuit providing said output feedback frequency signal based upon a majority vote of the sub-divide by N functions.

2. Apparatus for implementing a fault tolerant PLL circuit as recited in claim 1 wherein said stored factors of each of the plurality of sub-divide by N functions are compared by said compare and reload logic.

3. Apparatus for implementing a fault tolerant PLL circuit as recited in claim 2 wherein said compare and reload logic identifies a different value stored in one of the plurality of sub-divide by N functions; and responsive to identifying said different value, said compare and reload logic loads said stored factor from the other sub-divide by N functions into the one sub-divide by N function.

4. Apparatus for implementing a fault tolerant PLL circuit as recited in claim 1 wherein said compare and reload logic compares a predefined counter event from each said counter circuitry of said plurality of sub-divide by N functions.

5. Apparatus for implementing a fault tolerant PLL circuit as recited in claim 1 includes a phase detector receiving an input reference frequency signal; and said divide by N circuit provides said output feedback frequency signal to said phase detector.

6. Apparatus for implementing a fault tolerant PLL circuit as recited in claim 5 includes a loop filter coupled to said phase detector.

7. Apparatus for implementing a fault tolerant PLL circuit as recited in claim 5 includes a Voltage Controlled Oscillator (VCO) coupled to said phase detector; said VCO providing a multiplied reference frequency to said divide by N circuit.

8. Apparatus for implementing a fault tolerant PLL circuit as recited in claim 1 wherein said plurality of sub-divide by N functions includes three sub-divide by N functions, and wherein said voter circuit provides said output feedback frequency signal based upon at least two matching feedback frequency signals from said three sub-divide by N functions.

9. A method for implementing a fault tolerant phase locked loop (PLL) circuit comprising:

providing a plurality of sub-divide by N functions, providing compare and reload logic coupled to each said sub-divide by N function, and each of said plurality of sub-divide by N functions including a counter circuitry and an N register storing a factor for dividing a received frequency signal, and a voter circuit coupled to each of said sub-divide by N functions to define a divide by N circuit,

generating a feedback frequency signal with each said sub-divide by N function;

comparing a predefined counter event from each said counter circuitry of said plurality of sub-divide by N functions using said compare and reload logic,

responsive to identifying a failed counter event, synchronizing said counter circuitry of the plurality of sub-divide by N functions using said compare and reload logic;

applying said feedback frequency signals from each of said sub-divide by N functions to said voter circuit; and

providing an output feedback frequency signal based upon a majority vote of said feedback frequency signals with said voter circuit.

10. A method for implementing a fault tolerant PLL circuit as recited in claim 9 further includes comparing said stored factors of each of the plurality of sub-divide by N functions using said compare and reload logic.

11. A method for implementing a fault tolerant PLL circuit as recited in claim 10 further includes responsive to identifying a different value stored in one of the plurality of sub-divide by N functions, said compare and reload logic loads said stored factor from the other sub-divide by N functions into the one sub-divide by N function.