Method and circuit using boundary scan cells for design library analysis

1. A boundary scan register circuit, comprising:

a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch;

means for isolating said boundary scan cells into two or more boundary scan segments, each boundary scan segment containing a different set of said boundary scan cells; and

means for characterizing signal propagation speed through each said boundary scan segment.

2. A boundary scan register circuit, comprising:

a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch;

means for isolating said boundary scan cells into one or more boundary scan segments, each boundary scan segment containing a different set of said boundary scan cells; and

means for characterizing signal propagation through each said boundary scan segment, said means for characterizing signal propagation through each said boundary scan segment including a corresponding oscillator circuit comprising each said latch in each said boundary scan segment.

3. The boundary scan register circuit of claim 2 , wherein said latch is a flushable latch.

4. The boundary scan register circuit of claim 2 , wherein said latch is a flushable D flip-flop.

5. The boundary scan register circuit of claim 2 , wherein a circuit implementation of said latch in each boundary scan cell of a first boundary scan segment is different from a corresponding circuit implementation of said latch in each boundary scan cell of a second boundary scan segment.

6. The boundary scan register circuit of claim 2 , wherein said latch in each boundary scan cell of a first boundary scan segment includes devices selected from a first process technology device library and said latch in each boundary scan cell of a second boundary scan segment includes devices selected from a second and different process technology device library.

7. The boundary scan register circuit of claim 6 , wherein said first and second process technology device libraries include elements dependently selected from the group consisting of transistors having nominal design threshold voltages, sub-nominal design threshold voltages, super-nominal design threshold voltages, nominal design gate dielectric thickness, sub-nominal design gate dielectric thickness, super-nominal design gate dielectric thickness, nominal design channel length, sub-nominal design channel length and super-nominal design channel length.

8. The boundary scan register circuit of claim 2 , wherein:

said means for characterizing signal propagation through each said boundary scan segment further includes a corresponding cycle counter coupled to each said oscillator circuit; and

said means for isolating said boundary scan cells into one or more boundary scan segments includes a corresponding multiplexer in each boundary scan segment, a first input of each multiplexer coupled to a test data input pad or a test data output pin of a last boundary scan cell of an immediately previous boundary scan segment, a second input of said multiplexer coupled to a test data output pin of a corresponding last boundary scan cell of each boundary scan segment and an output of said multiplexer coupled to a test data input pin of a corresponding first boundary scan latch of each boundary scan segment.

9. A method of characterizing elements of a boundary scan cell, comprising:

providing a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch;

isolating said boundary scan cells into two or more boundary scan segments, each boundary scan segment containing a different set of said boundary scan cells; and

characterizing signal propagation speed through each said boundary scan segment.

10. A method of characterizing elements of a boundary scan cell, comprising:

providing a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch;

isolating said boundary scan cells into one or more boundary scan segments, each boundary scan segment containing a different set of said boundary scan cells; and

characterizing signal propagation through each said boundary scan segment, said characterizing signal propagation through each said boundary scan segment including providing a corresponding oscillator circuit comprising each said latch in each said boundary scan segment.

11. The method of characterizing of claim 10 , wherein said latch is a flushable latch.

12. The method of characterizing of claim 10 , wherein said latch is a flushable D flip-flop.

13. The method of characterizing of claim 10 , wherein a circuit implementation of said latch in each boundary scan cell of a first boundary scan segment is different from a corresponding circuit implementation of said latch in each boundary scan cell of a second boundary scan segment.

14. The method of characterizing of claim 10 , wherein said latch in each boundary scan cell of a first boundary scan segment includes devices selected from a first process technology device library and said latch in each boundary scan cell of a second boundary scan segment includes devices selected from a second and different process technology device library.

15. The method of characterizing of claim 14 , wherein said first and second process technology device libraries include elements dependently selected from the group consisting of transistors having nominal design threshold voltages, sub-nominal design threshold voltages, super-nominal design threshold voltages, nominal design gate dielectric thickness, sub-nominal design gate dielectric thickness, super-nominal design gate dielectric thickness, nominal design channel length, sub-nominal design channel length and super-nominal design channel length.

16. The method of characterizing of claim 10 , wherein:

characterizing signal propagation through each said boundary scan segment further includes providing a corresponding cycle counter coupled to each said oscillator circuit; and

isolating said boundary scan cells into one or more boundary scan segments includes providing a corresponding multiplexer in each boundary scan segment, a first input of each multiplexer coupled to a test data input pad or a test data output pin of a last boundary scan cell of an immediately previous boundary scan segment, a second input of said multiplexer coupled to a test data output pin of a corresponding last boundary scan cell of each boundary scan segment and an output of said multiplexer coupled to a test data input pin of a corresponding first boundary scan latch of each boundary scan segment.

17. A method of characterizing elements of a boundary scan cell of a boundary scan register used for testing interconnections of an integrated circuit chip, comprising:

providing a set of boundary scan cells connected in series to form said boundary scan register, a test data output pin of each previous boundary scan cell of said boundary scan register coupled to a test data input pin of an immediately subsequent boundary scan cell of said boundary scan register, each boundary scan cell coupled between a different integrated circuit chip input/output pad and a corresponding core logic circuit pin of said core logic circuit, each boundary scan cell having a latch, each said latch having a latch mode and a flush mode;

isolating said boundary scan cells into two or more boundary scan segments, each boundary scan segment containing a different sub-set of said set of boundary scan cells; and

characterizing signal propagation through each said boundary scan segment.

18. The method of claim 17 , further including, in a normal operating mode of said integrated circuit chip:

for each boundary scan cell, coupling corresponding integrated circuit chip input/output pads to corresponding core logic circuit pins without passing through said latch of said boundary scan cell.

19. The method of claim 17 , further including, in a process technology device library characterization mode of said integrated circuit chip:

for each boundary scan segment, coupling said latch of each said boundary scan cell between a corresponding test data input pin and a corresponding test data output pin;

for each boundary scan segment, coupling a test data input of a first boundary scan cell to a test data output pin of a last boundary scan cell; and

setting each said latch to flush mode.

20. The method of claim 17 : wherein a circuit implementation of latches in each boundary scan cell of a first boundary scan segment of said one or more boundary scan segments is different from a corresponding circuit implementation of said latches in each boundary scan cell of a second boundary scan segment of said one or more boundary scan segments.