Driver for multi-voltage island/core architecture
View Patent ↗A system and method for providing a driver for a multi-voltage island/core architecture of an integrated circuit chip are provided. A complementary metal oxide semiconductor (CMOS) inverter is built with a high threshold voltage p-channel field-effect transistor (hi-Vt PFET) and a regular threshold voltage n-channel field-effect transistor (NFET), which uses the maximum positive voltage supply (Vdd) on the chip. The threshold voltage of the hi-Vt PFET is determined based on the maximum Vdd, the Vdd of the Voltage island/core that drives the CMOS inverter, and a subthreshold leakage current requirement of the hi-Vt PFET.
1. A system for providing a driver for a multi-voltage island/core architecture of an integrated circuit (IC) chip, the system comprising:
a p-channel field-effect transistor (PFET) and an n-channel field-effect transistor (NFET), the PFET and the NFET being coupled together to form a complementary metal-oxide semiconductor (CMOS) inverter;
wherein a gate pin of the PFET and a gate pin of the NFET are coupled to an output of a first voltage island/core of the multi-voltage island/core architecture; and wherein a source pin of the PFET is coupled to a maximum positive voltage supply (Vdd) on the IC chip; and wherein a threshold voltage of the PFET is determined based on the maximum Vdd, a first Vdd of the first voltage island/core, and a leakage current requirement of the PFET.
2. The system of claim 1 , wherein the threshold voltage of the PFET is determined using the equation:
Vt=Vdd max− Vdd 1 +S *log [( I vt *W/L )/ I off ],
where Vt denotes the threshold voltage; I off denotes the leakage current requirement; I vt denotes a current at threshold voltage of the PFET; S denotes a threshold slope factor of the PFET; W/L denotes a width/length ratio of the PFET; Vddmax denotes the maximum Vdd; and Vdd 1 denotes the first Vdd.
3. The system of claim 1 , wherein a drain pin of the PFET and a drain pin of the NFET are coupled to provide a logic state to a second voltage island/core.
4. A multi-voltage island/core architecture of an integrated circuit (IC) chip, the multi-voltage island/core architecture comprising:
a first voltage island/core and a second voltage island/core; and
a complementary metal-oxide semiconductor (CMOS) inverter including a p-channel field-effect transistor (PFET) and an n-channel field-effect transistor (NFET);
wherein a gate pin of the PFET and a gate pin of the NFET are coupled to an output of the first voltage island/core; and wherein a drain pin of the PFET and a drain pin of the NFET are coupled to provide a logic state to the second voltage island/core; and wherein a source pin of the PFET is coupled to a maximum positive voltage supply (Vdd) on the IC chip; and wherein a threshold voltage of the PFET is determined based on the maximum Vdd, a first Vdd of the first Voltage island/core, and a leakage current requirement of the PFET.
5. The architecture of claim 4 , wherein the threshold voltage of the PFET is determined using the equation:
Vt=Vdd max− Vdd 1 +S *log [( I vt *W/L )/ I off ],
where Vt denotes the threshold voltage; I off denotes the leakage current requirement; I vt denotes a current at threshold voltage of the PFET; S denotes a threshold slope factor of the PFET; W/L denotes a width/length ratio of the PFET; Vddmax denotes the maximum Vdd; and Vdd 1 denotes the first Vdd.
6. The architecture of claim 4 , wherein the maximum Vdd and the first Vdd are the same.
7. The architecture of claim 4 , wherein the maximum Vdd and the first Vdd are different than each other.
8. A method for providing a driver for a multi-voltage island/core architecture of an integrated circuit (IC) chip, the method comprising:
providing a complementary metal-oxide semiconductor (CMOS) inverter coupled between a first voltage island/core and a second voltage island/core of the multi-voltage island/core architecture, the CMOS inverter including a p-channel field-effect transistor (PFET) and an n-channel field-effect transistor (NFET), a gate pin of the PFET and a gate pin of the NFET being coupled to an output of the first voltage island/core, a drain pin of the PFET and a drain pin of the NFET being coupled to provide a logic state to the second voltage island/core, a source pin of the PFET being coupled to a maximum positive voltage supply (Vdd) on the IC chip; and
determining a threshold voltage of the PFET based on the maximum Vdd, a first Vdd of the first Voltage island/core, and a leakage current requirement of the PFET.
9. The method of claim 8 , wherein the threshold voltage of the PFET is determined using the equation:
Vt=Vdd max− Vdd 1 +S *log [( I vt *W/L )/ I off ],
where Vt denotes the threshold voltage; I off denotes the leakage current requirement; I vt denotes a current at threshold voltage of the PFET; S denotes a threshold slope factor of the PFET; W/L denotes a width/length ratio of the PFET; Vddmax denotes the maximum Vdd; and Vdd 1 denotes the first Vdd.
10. The method of claim 8 , wherein the providing step includes fabricating the PFET using ion implantation to adjust a body doping of a wafer to achieve the threshold voltage of the PFET.
11. The method of claim 8 , wherein the providing step includes increasing the threshold voltage of the PFET by applying a back bias voltage to the PFET body.