Differential amplifier offset voltage minimization independently from common mode voltage adjustment

1. A offset compensation circuit for differential amplifiers having first and second load impedances and first and second differential output signal terminal means and output terminal means comprising, in combination:

first and second adjustable current source means coupled to said differential amplifier means for supplying currents through said first and second load impedances, respectively, said first and second adjustable current source means including control input means for determining the amount of current to be supplied;

polarity determining means coupled to said first and second output terminal means for supplying an output signal indicative of polarity of an output signal across said differential output signal terminal means;

offset calibration means responsive to the output signal from said polarity determining means for supplying control signals to the control input means of said first and second adjustable current source means; and

means in said offset calibration means for varying said control signals until said output signal from the polarity determining means indicates a change in polarity.

2. The offset compensation means as claimed in claim 1 wherein said offset calibration means includes means coupled to said polarity determining means for latching said control signals atthe value which caused a change in polarity.

3. The offset compensation means as claimed in claim 2 wherein the offset calibration means includes sensing means responsive to the output signal from said polarity determining means for supplying an enabling signal, said enabling signal dependent on changes of polarity across said differential output signal means.

4. The offset compensation means as claimed in claim 3 wherein said offset calibration means include:

first and second counter means responsive to the enabling signal from said sensing means for supplying said control signals to the control input means of said first and second adjustable current source means; and

wherein said first and second adjustable current source means include digital-to-analog converter means.

5. The offset compensation means as claimed in claim 4 wherein said first and second counter means include:

preset means for initializing the count value in said first and second counter means in response to a signal indicative of starting a calibration phase; and

means for incrementing and decrementing said first and second counter means, respectively.

6. The offset compensation means as claimed in claim 3 wherein said offset calibration means includes:

counter means responsive to the enabling signal from said sensing means;

means for incrementing said counter means; and

converting means for converting the count value in said counter means to control signals from the offset calibration means.

7. The offset compensation means as claimed in claim 6 wherein said converting means includes:

digital-to-analog means for supplying voltage control signals to to the control input means of said first and second adjustable current source means; and

wherein said first and second adjustable current source means are voltage-to-current conversion means.

8. The offset compensation means as claimed in claim 7 including voltage inverter means responsive to said digital-to-analog converter means.

9. The offset compensation means as claimed in claim 8 including:

means for coupling said digital-to-analog means to the control input means of said first adjustable current source means; and

means for coupling said voltage inverter means to the control input means of said second adjustable current source means.

10. A method of minimizing offset voltage in a differential amplifier comprising the steps of:

supplying a pair of currents through load impedances of the differential amplifier;

controlling the pair of currents in opposing directions;

sensing the polarity of the differential amplifier's output signals during a calibration phase; and

latching the pair of currents at a value where the polarity of the differential amplifiers output signals changes.

11. The method of minimizing offset voltage in a differential amplifier as claimed in claim 10 including an additional step of varying the current during the calibration phase.

12. The method of minimizing offset voltage in a differential amplifier as claimed in claim 11 including an additional step of making the current vary in a stepwise fashion.

13. A method of minimizing an offset current in differential amplifiers comprising the steps of:

providing a pair of controllable opposing direction currents, one in each branch of a differential amplifier;

varying the strengths of the pair of controllable opposing direction currents;

sensing the differential amplifier's output signals' polarity; and

latching the pair of controllable opposing direction currents at a value where the polarity changes.