Heterogeneously integrated microsystem-on-a-chip
A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.
1. A microsystem-on-a-chip, comprising:
a bottom chip comprising one or more microsystem devices with associated input/output pads on the top surface of the bottom chip;
an interconnect layer on the top surface of the bottom chip, the interconnect layer comprising a compliant dielectric material and an interconnect structure embedded in the compliant dielectric material, the interconnect structure comprising one or more via capture pads connected to the associated input/output pads on the top surface of the bottom chip; and
a thin upper chip on the interconnect layer, the thin upper chip comprising one or more microsystem devices with associated input/output pads on the top surface of the thin upper chip that are connected to the one or more via capture pads in the interconnect layer by conductive vias through the thin upper chip.
2. The microsystem-on-a-chip of claim 1 , further comprising at least one additional stacked layer on the thin chip, each additional stacked layer comprising:
a stacked interconnect layer on the top surface of the thin upper chip, the stacked interconnect layer comprising a compliant dielectric material and an interconnect structure embedded in the compliant dielectric material, the interconnect structure comprising one or more via capture pads connected to the associated input/output pads on the top surface of the thin upper chip
a stacked thin chip on the stacked interconnect layer, the stacked thin chip comprising one or more microsystem devices with associated input/output pads on the top surface of the stacked thin chip that are connected to the one or more via capture pads in the stacked interconnect layer by conductive vias through the stacked thin chip.
3. The microsystem-on-a-chip of claim 1 , wherein the interconnect layer has a thickness of less than 50 microns.
4. The microsystem-on-a-chip of claim 1 , wherein the compliant dielectric material is a polymer.
5. The microsystem-on-a-chip of claim 4 , wherein the polymer is benzocyclobutene.
6. The microsystem-on-a-chip of claim 1 , wherein the thin upper chip has a thickness of less than 120 microns.
7. The microsystem-on-a-chip of claim 1 , wherein the interconnect structure further comprises at least one passive component.
8. The microsystem-on-a-chip of claim 7 , wherein the at least one passive component comprises a thin-film resistor.
9. The microsystem-on-a-chip of claim 7 , wherein the at least one passive component comprises a multi-layer capacitor.
10. The microsystem-on-a-chip of claim 7 , wherein the at least one passive component comprises a spiral inductor.
11. The microsystem-on-a-chip of claim 1 , wherein the interconnect structure comprises copper.
12. The microsystem-on-a-chip of claim 1 , wherein the one or more via capture pads are sized to control the alignment tolerance of the thin upper chip.