IP Library Granted Patent US 7,084,428
Granted Patent B2
US 7,084,428 · App. 10/717,503 · Granted Aug 1, 2006

Transistor, integrated circuit, electro-optic device, electronic instrument and method of manufacturing a transistor

Assignee: Seiko Epson Corporation
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Quick Facts
Patent No.
US 7,084,428
App. No.
10/717,503
Granted
Aug 1, 2006
Kind
B2
Abstract

There is provided a transistor and a method of manufacturing this transistor that allow a high degree of freedom when designing a wiring structure and also allow an improvement in product quality to be achieved. The transistor includes a source area, a drain area, and a channel area, each of which are formed by semiconductor films, and also a gate insulating film and a gate electrode. The semiconductor film containing the source area and the semiconductor film containing the drain area are formed separately sandwiching both sides of an insulating member. The semiconductor film containing the channel area is formed on top of the insulating member.

Claims (40)

1. An active matrix substrate comprising:

a substrate;

a backing insulating layer on the substrate;

a source portion formed over the backing insulating layer;

a drain portion formed over the backing insulating layer;

a first insulating film formed over the backing insulating layer, the first insulating film separating the source portion and the drain portion;

a semiconductor layer formed on at least a part of the source portion, at least a part of the drain portion, and at least a part of the first insulating film;

a gate insulating layer formed over the semiconductor layer; and

a gate electrode formed over the gate insulating layer.

2. The active matrix substrate according to claim 1 , further comprising a second insulating film formed around the semiconductor layer, the second insulating film not being formed over the semiconductor layer.

3. The active matrix substrate according to claim 1 , further comprising a source electrode contacting the source portion via a first contact hole, the first contact hole being formed at least in the gate insulating layer.

4. The active matrix substrate according to claim 1 , further comprising a drain electrode contacting the drain portion via a second contact hole, the second contact hole being formed at least in the gate insulating layer.

5. The active matrix substrate according to claim 1 , wherein a thickness of the first insulating film is larger than a thickness of the source portion.

6. The active matrix substrate according to claim 1 , wherein the first insulating film is a separation wall surrounding the source portion.

7. The active matrix substrate according to claim 1 , wherein the first insulating film includes a silicon oxide.

8. The active matrix substrate according to claim 1 , wherein a thickness of a first part of the semiconductor layer on the source portion is different from a thickness of a second part of the semiconductor layer on the first insulating film.

9. The active matrix substrate according to claim 1 , wherein a thickness of a first part of the semiconductor layer on the source portion is thinner than a thickness of a second part of the semiconductor layer on the first insulating film.

10. The active matrix substrate according to claim 1 , wherein the gate electrode overlaps at least a part of the source portion.

11. An electro-optic device having the active matrix substrate according to claim 1 .

12. An electronic instrument having the electro-optic device according to claim 11 .

13. An active matrix substrate comprising:

an insulating substrate;

a source portion formed over the insulating substrate;

a drain portion formed over the insulating substrate;

a first insulating film formed over the insulating substrate, the first insulating film separating the source portion and the drain portion;

a semiconductor layer formed on at least a part of the source portion, at least a part of the drain portion, and at least a part of the first insulating film;

a gate insulating layer formed over the semiconductor layer; and

a gate electrode formed over the gate insulating layer.

14. The active matrix substrate according to claim 13 , further comprising a second insulating film formed around the semiconductor layer, the second insulating film not being formed over the semiconductor layer.

15. The active matrix substrate according to claim 13 , further comprising a source electrode contacting the source portion via a first contact hole, the first contact hole being formed at least in the gate insulating layer.

16. The active matrix substrate according to claim 13 , further comprising a drain electrode contacting the drain portion via a second contact hole, the second contact hole being formed at least in the gate insulating layer.

17. The active matrix substrate according to claim 13 , wherein a thickness of the first insulating film is larger than a thickness of the source portion.

18. The active matrix substrate according to claim 13 , wherein the first insulating film is a separation wall surrounding the source portion.

19. The active matrix substrate according to claim 13 , wherein the first insulating film includes a silicon oxide.

20. The active matrix substrate according to claim 13 , wherein a thickness of a first of the semiconductor layer on the source portion is different from a thickness of a second part of the semiconductor layer on the first insulating film.

21. The active matrix substrate according to claim 13 , wherein a thickness of a first part of the semiconductor layer on the source portion is thinner than a thickness of a second part of the semiconductor layer on the first insulating film.

22. The active matrix substrate according to claim 13 , wherein the gate electrode overlaps at least a part of the source portion.

23. An electro-optic device having the active matrix substrate according to claim 13 .

24. The active matrix substrate according to claim 13 , further comprising:

a backing insulating layer on the insulating substrate, wherein the source portion, the drain portion and the first insulating film are formed on the backing insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2004
From: YUDASAKA, ICHIO; FURUSAWA, MASAHIRO; AOKI, TAKASHI
To: SEIKO EPSON CORPORATION
Reel/Frame 015300/0614 →
Priority Claims (1)
JP 2002-351112 · Dec 3, 2002 · national
Continuity (1)
Related Publication 20050029591A1 · Feb 10, 2005