Semiconductor device and method of fabricating the same
View Patent ↗A semiconductor device having an interlayer insulation film with a low capacitance and a method of fabricating the same are disclosed. An example semiconductor device having a multi-layered metal wire structure includes first and second interlayer insulation films provided between lower metal wire layers and upper metal wire layers. The example semiconductor device also includes air gaps formed in the first interlayer insulation film at an interlevel between the upper and lower metal wire layers and via holes connecting the upper and lower metal wire layers.
1. A method of fabricating a semiconductor device, comprising:
forming a first interlayer insulation film above a lower insulation film on a top surface of a semiconductor substrate where an individual element including lower metal wire layers is formed;
forming a first mask film and a second mask film on the first interlayer insulation film sequentially;
forming a first etch mask to be used to form air gaps by selectively etching the second mask film;
depositing a third mask film on the first etch mask and the first mask film;
forming a second etch mask by etching the third mask film and exposed the first mask film, wherein the second etch mask is made from the third mask film remaining on side walls of the first etch mask and the first mask film remaining below the first etch mask and the third mask film;
removing the first etch mask and simultaneously forming open pores in the first interlayer insulation film by etching the first etch mask and exposed the first interlayer insulator film using the second etch mask;
forming air gaps comprising closed pores in the first interlayer film at an interlevel between upper metal wire layers and the lower metal wire layers by forming a second interlayer insulation film after removing the second etch mask; and
forming via holes to expose the lower metal wire layers by selectively removing the first and second interlayer insulation films, filling metal material in the via holes, and forming the upper metal wire layers.
2. A method as defined in claim 1 , wherein the first and second interlayer insulation layers are made from TEOS family material.
3. A method as defined in claim 1 , wherein the first mask film have different etch rate from the second and third mask films.
4. A method as defined in claim 3 , wherein the first mask film is made from an oxide film.
5. A method as defined in claim 3 , wherein the first mask film is made from same material as the first interlayer insulator film.
6. A method as defined in claim 1 , wherein the second and third mask films have a substantially similar etch rate.
7. A method as defined in claim 6 , wherein the second and third mask films are made from a nitride film.
8. A method as defined in claim 1 , wherein etching to form the second etch mask is performed by isotropic etching.