CMOS device having retrograde n-well and p-well
View Patent ↗A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs formed in the n-well adjacent the nwell-pwell interface. The thinned mask is then removed, a p-well mask is put in place, and the remainder of the p-well implants are carried out.
1. A CMOS device having FETs with effective channel lengths less than or equal to approximately 0.11 um formed in adjacent, retrograde nwells and pwells, wherein threshold voltages of FETs formed with approximately 1.5 um of an interface between said nwells and pwells are constant within approximately 10 mV.
2. The CMOS device of claim 1 , wherein p-type dopant regions are located immediately below said retrograde nwells.
3. The CMOS device of claim 1 , wherein said retrograde nwells comprise a first n-type dopant region having a first dopant level, a second n-type dopant region immediately above said first n-type dopant region and having a second dopant level, and a third n-type dopant region immediately above said second n-type dopant region and having a third dopant level.
4. The CMOS device of claim 3 , wherein the first dopant level is greater than the second dopant level.
5. The CMOS device of claim 4 , wherein the second dopant level is greater than the third dopant level.
6. The CMOS device of claim 5 further comprising a p-type dopant region immediately below the first n-type dopant region.
7. The CMOS device of claim 1 , wherein said retrograde pwells comprise a first p-type dopant region having a first dopant level, a second p-type dopant region immediately above said first p-type dopant region and having a second dopant level, and a third p-type dopant region immediately above said second p-type dopant region and having a third dopant level.
8. The CMOS device of claim 3 , wherein said retrograde pwells comprise a first p-type dopant region having a first dopant level, a second p-type dopant region immediately above said first p-type dopant region and having a second dopant level, and a third p-type dopant region immediately above said second p-type dopant region and having a third dopant level.
9. The CMOS device of claim 8 , wherein said first p-type dopant region is located substantially adjacent to said first n-type dopant region.