Block redundancy implementation in heirarchical RAM'S
View Patent ↗The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one redundant predecoder adapted to be shifted in for at least one active predecoder of a plurality of predecoders adapted to be shifted out.
1. A method of providing redundancy in a memory structure, comprising:
shifting out at least one first predecoder of a pluarality of first predecoders; and shifting in a second predecoder.
2. The method of claim 1 , comprising shifting predecoded lines coupled to at least one of said first and second predecoders.
3. The method of claim 1 , comprising using shifting circuitry coupled to at least one of said first and second predecoders.
4. The method of claim 1 comprising at least one higher address predecoded line coupled to at least said second predecoder.
5. The method of claim 4 comprising at least one lower address predecoded line coupled to at least said active predecoder and paired with at least one higher address predecoded line.
6. A method of providing redundancy in a hierarchical memory structure, comprising:
identifying at least one first predecoder of a plurality of first predecoders;
shifting out said identified at least one first predecoder; and
shifting in at least one second predecoder.
7. The method of claim 6 comprising shifting predecoded lines coupled to at least one of said first and second predecoders.
8. The method of claim 6 comprising using shifting circuitry coupled to at least one of said first and second predecoders.
9. The method of claim 6 comprising at least one higher address predecoded line coupled to at least one of said first and second predecoders.
10. The method of claim 9 comprising at least one lower address predecoded line coupled to at least one of said first and second predecoders and paired with said at least one higher address predecoded line.
11. The method of claim 6 comprising at least one of said first predecoders adapted to fire for current address mapping.
12. The method of claim 6 comprising said at least one second predecoder adapted to fire for previous address mapping.
13. The method of claim 6 comprising shifting in said second predecoder using shift circuitry.
14. A method of providing redundancy in a hierarchical memory structure, comprising:
identifying at least one predecoder as a predecoder for shifting out; and
shifting out said identified at least one predecoder.
15. The method of claim 14 comprising shifting in at least one other predecoder.
16. The method of claim 15 comprising shifting predecoded lines coupled to at least one of said at least one predecoder and said at least one other predecoder.
17. The method of claim 15 comprising using shifting circuitry coupled to at least one of said at least one predecoder and said at least one other predecoder.
18. The method of claim 15 comprising at least one higher address predecoded line coupled to at least one of said at least one predecoder and said at least one other predecoder.
19. The method of claim 18 comprising at least one lower address predecoded line coupled to at least one of said at least one predecoder and said at least one other predecoder and paired with said at least one higher address predecoded line.
20. The method of claim 14 comprising said at least one predecoder adapted to fire for current address mapping.
21. The method of claim 14 comprising said at least one predecoder adapted to fire for previous address mapping.
22. The method of claim 15 comprising shifting in said at least one other predecoder using shift circuitry.
23. A method of providing redundancy in a memory structure, comprising:
identifying at least one predecoder as a predecoder for shifting out; and
shifting in at least one other predecoder.
24. The method of claim 23 , comprising shifting predecoded lines coupled to at least one of said at least one predecoder and said at least one other predecoder.
25. The method of claim 23 , comprising using shift circuitry coupled to at least one of said at least one predecoder and said at least one other predecoder.
26. The method of claim 23 comprising at least one higher address predecoded line coupled to at least one of said at least one predecoder and said at least one other predecoder.
27. The method of claim 26 comprising at least one lower address predecoded line coupled to at least one of said at least one predecoder and said at least one other predecoder and paired with said at least one higher address predecoded line.
28. The method of claim 23 comprising said at least one predecoder adapted to fire for current address mapping.
29. The method of claim 23 comprising said at least one predecoder adapted to fire for previous address mapping.
30. The method of claim 23 comprising shifting in said at least one other predecoder using shift circuitry.