Oxide/nitride stacked in FinFET spacer process
View Patent ↗In a FinFET integrated circuit, the fins are formed with a body thickness in the body area and then thickened in the source/drain area outside the body to improve conductivity. The thickening is performed with epitaxial deposition while the gates are covered by a composite gate cover layer to prevent thickening of the gates, which may short the gate to the source/drain.
1. A method of forming a FinFET comprising the steps of:
forming a set of fins having a fin height and a fin thickness on a silicon substrate;
forming a gate, having a gate height greater than said fin height and intersecting said fin in a body area and separated therefrom by a gate insulator;
depositing a first temporary material up to a first level above the top of said fin and below said gate height;
forming a conformal layer over said gate;
using said conformal layer as a hardmask, etching said temporary material, thereby forming a composite gate cover over said gate and exposing sides of said fins; and
increasing said fin thickness while said gate is isolated from said set of fins by said gate cover.
2. A method according to claim 1 , in which said fins are formed from silicon, said first temporary material is oxide and said conformal layer is nitride, whereby said composite layer comprises oxide in a lower portion and nitride in an upper portion.
3. A method according to claim 2 , further comprising a step of etching said oxide in said lower portion with a method selective to nitride, thereby reducing a thickness of said oxide in said lower portion.
4. A method according to claim 3 , in which said oxide in said lower portion is reduced to a first thickness in N-type FinFETs and to a second thickness of P-type FinFETs.
5. A method according to claim 1 , in which said step of increasing said fin thickness is performed by epitaxial growth on poly fins.
6. A method according to claim 5 , in which said fins are formed from silicon, said first temporary material is oxide and said conformal layer is nitride, whereby said composite layer comprises oxide in a lower portion and nitride in an upper portion.
7. A method according to claim 6 , further comprising a step of etching said oxide in said lower portion with a method selective to nitride, thereby reducing a thickness of said oxide in said lower portion.
8. A method according to claim 7 , in which said oxide in said lower portion is reduced to a first thickness in N-type FinFETs and to a second thickness in P-type FinFETs.
9. A method according to claim 1 , in which said silicon substrate is a SOI substrate having a device layer of silicon above a layer of buried insulator and said fins are formed in said device layer.
10. A method according to claim 9 , in which said fins are formed from silicon, said first temporary material is oxide and said conformal layer is nitride, whereby said composite layer comprises oxide in a lower portion and nitride in an upper portion.
11. A method according to claim 10 , further comprising a step of etching said oxide in said lower portion with a method selective to nitride, thereby reducing a thickness of said oxide in said lower portion.
12. A method according to claim 11 , in which said oxide in said lower portion is reduced to a first thickness in N-type FinFETs and to a second thickness in P-type FinFETs.
13. A method of forming a FinFET comprising the steps of:
forming a set of fins having a fin height and a fin thickness on a silicon substrate;
forming a gate, having a gate height greater than said fin height and intersecting said fin in a body area and separated therefrom by a gate insulator;
depositing a first temporary material up to a first level at said gate height;
recessing said temporary material to a height below said gate height and above said fins;
forming a conformal cap over said gates and fins:
using said conformal cap as a hardmask, etching said temporary material, thereby exposing said fins; and
increasing said fin thickness while said gate is isolated from said set of fins by said cap.
14. A method according to claim 13 , in which said fins are formed from silicon, said first temporary material is oxide and said conformal layer is nitride, whereby said composite layer comprises oxide in a lower portion and nitride in an upper portion.
15. A method according to claims 14 , further comprising a step of etching said oxide in said lower portion with a method selective to nitride, thereby reducing a thickness of said oxide in said lower portion.
16. A method according to claim 15 , in which said oxide in said lower portion is reduced to a first thickness in N-type FinFETs and to a second thickness of P-type FinFETs.
17. A method according to claim 13 , in which said step of increasing said fin thickness is performed by epitaxial growth on poly fins.
18. A method according to claim 17 , in which said fins are formed from silicon, said first temporary material is oxide and said conformal layer is nitride, whereby said composite layer comprises oxide in a lower portion and nitride in an upper portion.
19. A method according to claim 18 , further comprising a step of etching said oxide in said lower portion with a method selective to nitride, thereby reducing a thickness of said oxide in said lower portion.
20. A method according to claim 19 , in which said oxide in said lower portion is reduced to a first thickness in N-type FinFETs and to a second thickness in P-type FinFETs.
21. A method according to claim 13 , in which said silicon substrate is a SOI substrate having a device layer of silicon above a layer of buried insulator and said fins are formed in said device layer.
22. A method according to claim 21 , in which said fins are formed from silicon, said first temporary material is oxide and said conformal layer is nitride, whereby said composite layer comprises oxide in a lower portion and nitride in an upper portion.
23. A method according to claim 22 , further comprising a step of etching said oxide in said lower portion with a method selective to nitride, thereby reducing a thickness of said oxide in said lower portion.
24. A method according to claim 23 , in which said oxide in said lower portion is reduced to a first thickness in N-type FinFETs and to a second thickness in P-type FinFETs.