Patent Assignment
Reel/Frame 052620/0961
Assignment of Assignor's Interest
Recorded: 2020-05-11
Pages: 20
Assignor
INTERNATIONAL BUSINESS MACHINES CORPORATION
Executed: 2020-03-06
Assignee
ELPIS TECHNOLOGIES INC.
1891 ROBERTSON ROAD, SUITE 100, OTTAWA, K2H 5B7, CANADA
Covered Properties
(320)
Method of making mosfet with high dielectric constant gate insulator and minimum overlap capacitance
Patent:
6,271,094 →
Application:
09/503,926 →
Mosfet with high dielectric constant gate insulator and minimum overlap capacitance
High Speed Ge Channel Heterostructures for Field Effect Devices
Patent:
7,145,167 →
Application:
09/936,320 →
A Process of Insulating a Semiconductor Device Using a Polymeric Material
Silicon Chip Carrier with Through-Vias Using Laser Assisted Chemical Vapor Deposition of Conductor
Oxide/Nitride Stacked in Finfet Spacer Process
Method for Improved Process Latitude by Elongated via Integration
Method of Forming Gate Stack for Semiconductor Electronic Device
Methods of Selective Deposition of Fine Particles Onto Selected Regions of a Substrate
Device and Method for Improving Interface Adhesion in Thin Film Structures
Dielectric Material
Method for Improved Process Latitude by Elongated via Integration
High Speed Ge Channel Heterostructures for Field Effect Devices
Circuit Structure with Low Dielectric Constant Regions and Method of Forming Same
Microelectronic Circuit Structure with Layered Low Dielectric Constant Regions and Method of Forming Same
Circuit Structure with Low Dielectric Constant Regions
High Speed Ge Channel Heterostructures for Field Effect Devices
Microelectronic Circuit Structure with Layered Low Dielectric Constant Regions
Methods of Selective Deposition of Fine Particles Onto Selected Regions of a Substrate
Selective Nanotube Growth Inside Vias Using an Ion Beam
High-K/Metal Gate Transistor with L-Shaped Gate Encapsulation Layer
Aqueous-Based Method of Forming Semiconductor Film and Photovoltaic Device Including the Film
Controlled Fin-Merging for Fin Type Fet Devices
Use of Metal Phosphorus in Metallization of Photovoltaic Devices and Method of Fabricating Same
Multiple Step Anneal Method and Semiconductor Formed by Multiple Step Anneal
Photovoltaic Cells with Copper Grid
Carbon Implant for Workfunction Adjustment in Replacement Gate Transistor
Replacement Gate Electrode with Multi-Thickness Conductive Metallic Nitride Layers
Techniques for Improving Bond Pad Performance
Method of Forming Semiconductor Film and Photovoltaic Device Including the Film
High-K/Metal Gate Transistor with L-Shaped Gate Encapsulation Layer
Replacement Gate Electrode with Multi-Thickness Conductive Metallic Nitride Layers
Carbon Implant for Workfunction Adjustment in Replacement Gate Transistor
Controlled Fin-Merging for Fin Type FET Devices
Trilayer SIT Process with Transfer Layer for FINFET Patterning
Multilayer Dielectric Structures for Semiconductor Nano-Devices
Hybrid ETSOI Structure to Minimize Noise Coupling from TSV
Magnetic Trap for Cylindrical Diamagnetic Materials
Self-Formation of High-Density Arrays of Nanostructures
Wafer Scale Epitaxial Graphene Transfer
Self-Aligned Structure for Bulk Finfet
Contact Structure Employing a Self-Aligned Gate Cap
Substrate Holder Assembly for Controlled Layer Transfer
Hybrid Extremely Thin Silicon-on-Insulator (ETSOI) Structure to Minimize Noise Coupling from TSV
Self-Formation of High-Density Arrays of Nanostructures
Magnetic Trap for Cylindrical Diamagnetic Materials
Trilayer SIT Process with Transfer Layer for FINFET Patterning
Multilayer Dielectric Structures for Semiconductor Nano-Devices
Contact Structure Employing a Self-Aligned Gate Cap
Controlled Spalling of Group Iii Nitrides Containing an Embedded Spall Releasing Plane
Replacement Gate Electrode with Multi-Thickness Conductive Metallic Nitride Layers
Dual Silicide Regions and Method for Forming the Same
Formation of Fins Having Different Heights in Fin Field Effect Transistors
Shallow Trench Isolation for End Fin Variation Control
Techniques for Fabricating Reduced-Line-Edge-Roughness Trenches for Aspect Ratio Trapping
Thin-Film Gallium Nitride Structures Grown on Graphene
Patent:
9,064,698 →
Application:
14/229,936 →
III-V, SiGe, or Ge Base Lateral Bipolar Transistor and CMOS Hybrid Technology
Hybrid Iii-V Technology to Support Multiple Supply Voltages and Off State Currents on Same Chip
Semiconductor Device Including Gate Channel Having Adjusted Threshold Voltage
Engineered Base Substrates for Releasing Iii-V Epitaxy Through Spalling
Self-Limiting Silicide in Highly Scaled Fin Technology
Symmetrical Bipolar Junction Transistor Array
Thin Film Interconnects with Large Grains
Device Isolation for III-V Substrates
Method of Fabricating Electrostatically Enhanced Fins and Stacked Nanowire Field Effect Transistors
Patent:
9,219,154 →
Application:
14/331,857 →
Lithography Using Interface Reaction
Techniques for Creating a Local Interconnect Using a SOI Wafer
Extended Contact Area Using Undercut Silicide Extensions
Multi-Chip Module with Rework Capability
Wafer Level Overmold for Three Dimensional Surfaces
Low External Resistance Channels in Iii-V Semiconductor Devices
Engineered Substrate and Device for Co-Integration of Strained Silicon and Relaxed Silicon
Patent:
9,209,065 →
Application:
14/483,907 →
Self-Forming Spacers Using Oxidation
Structure and Method for Advanced Bulk Fin Isolation
Double Aspect Ratio Trapping
Self-Cut Sidewall Image Transfer Process
Crystal Formation on Non-Lattice Matched Substrates
Lattice Matched Aspect Ratio Trapping to Reduce Defects in Iii-V Layer Directly Grown on Silicon
Magnetic Trap for Cylindrical Diamagnetic Materials
Semiconductor Device with Buried Local Interconnects
Multiple Vt in Iii-V Fets
Patent:
9,299,615 →
Application:
14/578,934 →
Multi-Orientation Soi Substrates for Co-Integration of Different Conductivity Type Semiconductor Devices
SiGe FINFET WITH IMPROVED JUNCTION DOPING CONTROL
Semiconductor Device Having Self-Aligned Gate Contacts
Charge Carrier Transport Facilitated by Strain
Silicon-Germanium Fin Formation
Type Iii-V and Type Iv Semiconductor Device Formation
Controlled Spalling Using a Reactive Material Stack
Patent:
9,324,566 →
Application:
14/587,972 →
Fabrication of Iii-V-on-Insulator Platforms for Semiconductor Devices
Method of Lateral Oxidation of Nfet and Pfet High-K Gate Stacks
Iii-V Cmos Integration on Silicon Substrate via Embedded Germanium-Containing Layer
Electrode Pair Fabrication Using Directed Self Assembly of Diblock Copolymers
Patent:
9,306,164 →
Application:
14/609,709 →
Nitridation on Hdp Oxide Before High-K Deposition to Prevent Oxygen Ingress
Reducing Substrate Bowing Caused by High Percentage Sige Layers
Formation of Strained Fins in a Finfet Device
Silicon Germanium-on-Insulator Formation by Thermal Mixing
Epitaxial Silicon Germanium Fin Formation Using Sacrificial Silicon Fin Templates
Finfet Having Controlled Dielectric Region Height
Multiple Threshold Voltage Trigate Devices Using 3D Condensation
Selective Dopant Junction for a Group Iii-V Semiconductor Device
Method to Improve Finfet Cut Overlay
Adjacent Strained <100> Nfet Fins and <110> Pfet Fins
Silicon-Germanium Finfet Device with Controlled Junction
Fin Trimming in a Double Sit Process
Techniques for Multiple Gate Workfunctions for a Nanowire Cmos Technology
Forming Multi-Stack Nanowires Using a Common Release Material
Silicon-On-Insulator Substrates Having Selectively Formed Strained and Relaxed Device Regions
Patent:
9,437,680 →
Application:
14/674,086 →
Finfet Including Varied Fin Height
Patent:
9,324,792 →
Application:
14/674,145 →
Finfet Devices with Multiple Channel Lengths
Preparation of Low Defect Density of Iii-V on Si for Device Fabrication
Method of Forming High-Density Arrays of Nanostructures
Self-Formation of High-Density Arrays of Nanostructures
Semiconductor Device Including Gate Channel Having Adjusted Threshold Voltage
Germanium Dual-Fin Field Effect Transistor
Shallow Trench Isolation for End Fin Variation Control
Self-Aligned Low Defect Segmented Iii-V Finfet
Patent:
9,293,374 →
Application:
14/737,738 →
Edram for Planar Iii-V Semiconductor Devices
Patent:
9,437,675 →
Application:
14/738,073 →
Method for Forming a Semiconductor Structure Containing High Mobility Semiconductor Channel Materials
Magnetic Trap for Cylindrical Diamagnetic Materials
Germanium Dual-Fin Field Effect Transistor
Silicon-On-Insulator Substrates Having Selectively Formed Strained and Relaxed Device Regions
Patent:
9,349,861 →
Application:
14/744,078 →
Preparation of Low Defect Density of Iii-V on Si for Device Fabrication
High Germanium Content Finfet Devices Having the Same Contact Material for Nfet and Pfet Devices
Patent:
9,449,885 →
Application:
14/744,887 →
Finfet Including Varied Fin Height
Patent:
9,362,178 →
Application:
14/745,736 →
Techniques for Forming Contacts for Active BEOL
Patent:
9,490,164 →
Application:
14/747,103 →
Tone Inverted Directed Self-Assembly (Dsa) Fin Patterning
Patent:
9,368,350 →
Application:
14/747,487 →
Compound Finfet Device Including Oxidized Iii-V Fin Isolator
Electrode Pair Fabrication Using Directed Self Assembly of Diblock Copolymers
Patent:
9,349,640 →
Application:
14/749,896 →
Method of Forming Field Effect Transistors (Fets) with Abrupt Junctions and Integrated Circuit Chips with the Fets
Implementing a Hybrid Finfet Device and Nanowire Device Utilizing Selective Sgoi
Reducing Autodoping of Iii-V Semiconductors by Atomic Layer Epitaxy (Ale)
Porous Silicon Relaxation Medium for Dislocation Free Cmos Devices
Cmos Fin Integration on Soi Substrate
Patent:
9,330,984 →
Application:
14/794,562 →
Method of Forming a Flexible Semiconductor Layer and Devices on a Flexible Carrier
Patent:
9,496,165 →
Application:
14/795,019 →
Methods to Reduce Debonding Forces on Flexible Semiconductor Films Disposed on Vapor-Releasing Adhesives
Patent:
9,455,179 →
Application:
14/795,216 →
Forming Multi-Stack Nanowires Using a Common Release Material
Dual Metal Contact Scheme for Cmos Devices
Patent:
9,478,468 →
Application:
14/795,524 →
Hetero-Integration of Iii-N Material on Silicon
Neutral Hard Mask and Its Application to Graphoepitaxy-Based Directed Self-Assembly (Dsa) Patterning
Integrated Circuit Having Strained Fins on Bulk Substrate
Patent:
9,524,969 →
Application:
14/811,887 →
Field Effect Transistor Contacts
Patent:
9,484,264 →
Application:
14/812,330 →
Porous Fin as Compliant Medium to Form Dislocation-Free Heteroepitaxial Films
Wafer Scale Epitaxial Graphene Transfer
Complementary Heterogeneous Mosfet Using Global Sige Substrate and Hard-Mask Memorized Germanium Dilution for Nfet
Patent:
9,484,266 →
Application:
14/817,549 →
Lattice Matched Aspect Ratio Trapping to Reduce Defects in Iii-V Layer Directly Grown on Silicon
Overhang Hardmask to Prevent Parasitic Epitaxial Nodules at Gate End During Source Drain Epitaxy
Method and Structure for Forming Finfet Cmos with Dual Doped Sti Regions
Cmos Compatible Fuse or Resistor Using Self-Aligned Contacts
P-Fet with Graded Silicon-Germanium Channel
Chemoepitaxy-Based Directed Self Assembly Process with Tone Inversion for Unidirectional Wiring
Epitaxial Lift-Off Process with Guided Etching
Self-Aligned Punch Through Stopper Liner for Bulk Finfet
Formation of SiGe Nanotubes
Method and Structure to Fabricate Closely Packed Hybrid Nanowires at Scaled Pitch
Fin Isolation on a Bulk Wafer
Metal Cap Protection Layer for Gate and Contact Metallization
Semiconductor Device Including Self-Aligned Gate Structure and Improved Gate Spacer Topography
Patent:
9,425,105 →
Application:
14/854,590 →
Magnetic Trap for Cylindrical Diamagnetic Materials
Highly Scaled Tunnel Fet with Tight Pitch and Method to Fabricate Same
Patent:
9,362,383 →
Application:
14/856,811 →
Dual-Semiconductor Complementary Metal-Oxide-Semiconductor Device
Patent:
9,437,614 →
Application:
14/858,964 →
Gate Planarity for Finfet Using Dummy Polish Stop
Patent:
9,490,253 →
Application:
14/863,079 →
Methods for Contact Formation for 10 Nanometers and Beyond with Minimal Mask Counts
Patent:
9,443,848 →
Application:
14/864,208 →
High-K Spacer for Extension-Free Cmos Devices with High Mobility Channel Materials
Tall Relaxed High Percentage Silicon Germanium Fins on Insulator
Patent:
9,378,952 →
Application:
14/871,008 →
Controlled Spalling Utilizing Vaporizable Release Layers
Patent:
9,496,128 →
Application:
14/884,262 →
Complementary Soi Lateral Bipolar Transistors with Backplate Bias
Patent:
9,536,788 →
Application:
14/886,927 →
Atomic Layer Doping and Spacer Engineering for Reduced External Resistance in Finfets
Patent:
9,490,332 →
Application:
14/918,737 →
Radiation Tolerant Device Structure
Patent:
9,515,171 →
Application:
14/920,046 →
Uniform Dielectric Recess Depth During Fin Reveal
Dual Silicide Liner Flow for Enabling Low Contact Resistance
Method and Structure for Forming Dually Strained Silicon
Patent:
9,472,671 →
Application:
14/929,312 →
Bonding Substrates Using Solder Surface Tension During Solder Reflow for Three Dimensional Self-Alignment of Substrates
Enhanced Defect Reduction for Heteroepitaxy by Seed Shape Engineering
Patent:
9,564,494 →
Application:
14/944,770 →
Compound Finfet Device Including Oxidized Iii-V Fin Isolator
Field Effect Transistor Including Strained Germanium Fins
Patent:
9,570,443 →
Application:
14/948,737 →
Self-Aligned Punch Through Stopper Liner for Bulk Finfet
Patent:
9,559,014 →
Application:
14/950,583 →
Semiconductor Device Including Self-Aligned Gate Structure and Improved Gate Spacer Topography
Patent:
9,548,250 →
Application:
14/951,726 →
Stop Layer Through Ion Implantation for Etch Stop
Patent:
9,627,263 →
Application:
14/953,461 →
Enhanced via Fill Material and Processing for Dual Damscene Integration
Method of Making a Semiconductor Device Having a Semiconductor Material on a Relaxed Semiconductor Including Replacing a Strained, Selective Etchable Material, with a Low Density Dielectric in a Cavity
Patent:
9,530,669 →
Application:
14/954,051 →
Localized Elastic Strain Relaxed Buffer
Patent:
9,570,298 →
Application:
14/963,356 →
Field Effect Transistor Contacts
Tall Strained High Percentage Silicon Germanium Fins for Cmos
Patent:
9,496,260 →
Application:
14/963,740 →
Overhang Hardmask to Prevent Parasitic Epitaxial Nodules at Gate End During Source Drain Epitaxy
Patent:
9,461,146 →
Application:
14/964,909 →
Selective Oxidation of Buried Silicon-Germanium to Form Tensile Strained Silicon Finfets
Patent:
9,570,590 →
Application:
14/965,880 →
Methods for Contact Formation for 10 Nanometers and Beyond with Minimal Mask Counts
Patent:
9,508,600 →
Application:
14/967,725 →
Method and Structure for Forming Finfet Cmos with Dual Doped Sti Regions
Patent:
9,530,698 →
Application:
14/968,230 →
Uniform Height Tall Fins with Varying Silicon Germanium Concentrations
Patent:
9,502,540 →
Application:
14/968,313 →
Composite Manganese Nitride / Low-K Dielectric Cap
Silicon-Germanium Semiconductor Devices and Method of Making
Patent:
9,595,449 →
Application:
14/976,522 →
Method of Fabricating Electrostatically Enhanced Fins and Stacked Nanowire Field Effect Transistors
Self-Aligned Low Defect Segmented Iii-V Finfet
Semiconductor Device Including Gate Channel Having Adjusted Threshold Voltage
Controlled Confined Lateral Iii-V Epitaxy
Patent:
9,437,427 →
Application:
14/984,546 →
Reactive Ion Etching Assisted Lift-Off Processes for Fabricating Thick Metallization Patterns with Tight Pitch
High Aspect Ratio Patterning of Hard Mask Materials by Organic Soft Masks
Decoupling Capacitor on Strain Relaxation Buffer Layer
Method of Making a Dual Strained Channel Semiconductor Device
Patent:
9,601,385 →
Application:
15/007,970 →
Strain Relaxed Buffer Layers with Virtually Defect Free Regions
Patent:
9,570,300 →
Application:
15/017,844 →
Multiple Vt in Iii-V Fets
Cmos Fin Integration on Soi Substrate
SiGe FINFET WITH IMPROVED JUNCTION DOPING CONTROL
Nitridation on Hdp Oxide Before High-K Deposition to Prevent Oxygen Ingress
Use of Metal Phosphorus in Metallization of Photovoltaic Devices and Method of Fabricating Same
Structure and Method for Advanced Bulk Fin Isolation
Structure and Method for Advanced Bulk Fin Isolation
Highly Scaled Tunnel Fet with Tight Pitch and Method to Fabricate Same
Highly Scaled Tunnel FET With Tight Pitch and Method to Fabricate Same
Device Isolation for Iii-V Substrates
Self-Limiting Silicide in Highly Scaled Fin Technology
Self-Formation of High-Density Arrays of Nanostructures
Epitaxial Silicon Germanium Fin Formation Using Sacrificial Silicon Fin Templates
Fabrication of Iii-V-on-Insulator Platforms for Semiconductor Devices
Uniform Height Tall Fins with Varying Silicon Germanium Concentrations
Patent:
9,496,186 →
Application:
15/085,068 →
Tone Inverted Directed Self-Assembly (Dsa) Fin Patterning
Complementary Heterogeneous Mosfet Using Global Sige Substrate and Hard-Mask Memorized Germanium Dilution for Nfet
Dual-Semiconductor Complementary Metal-Oxide-Semiconductor Device
Methods to Reduce Debonding Forces on Flexible Semiconductor Films Disposed on Vapor-Releasing Adhesives
Methods to Reduce Debonding Forces on Flexible Semiconductor Films Disposed on Vapor-Releasing Adhesives
Integrated Circuit Having Strained Fins on Bulk Substrate and Method to Fabricate Same
Methods to Reduce Debonding Forces on Flexible Semiconductor Films Disposed on Vapor-Releasing Adhesives
Method of Forming a Flexible Semiconductor Layer and Devices on a Flexible Carrier
Method of Forming a Flexible Semiconductor Layer and Devices on a Flexible Carrier
Method of Forming a Flexible Semiconductor Layer and Devices on a Flexible Carrier
Method of Forming a Flexible Semiconductor Layer and Devices on a Flexible Carrier
Semiconductor Device Including a Strain Relief Buffer
Type Iii-V and Type Iv Semiconductor Device Formation
Shallow Trench Isolation for Semiconductor Devices
Patent:
9,698,043 →
Application:
15/161,182 →
Double Aspect Ratio Trapping
Double Aspect Ratio Trapping
Magnetic Trap for Cylindrical Diamagnetic Materials
Controlled Spalling Utilizing Vaporizable Release Layers
Cmos Compatible Fuse or Resistor Using Self-Aligned Contacts
Wafer Stacking for Integrated Circuit Manufacturing
Semiconductor Device Having Self-Aligned Gate Contacts
Selective Oxidation of Buried Silicon-Germanium to Form Tensile Strained Silicon Finfets
Field Effect Transistor Including Strained Germanium Fins
Gate Planarity for Finfet Using Dummy Polish Stop
Finfet Having Controlled Dielectric Region Height
Germanium Dual-Fin Field Effect Transistor
Selective Dopant Junction for a Group Iii-V Semiconductor Device
Complementary Heterogeneous MOSFET Using Global SiGe Substrate And Hard-Mask Memorized Germanium Dilution For NFET
Silicon-Germanium Fin Formation
Controlled Confined Lateral Iii-V Epitaxy
Silicon Germanium-on-Insulator Formation by Thermal Mixing
Silicon Germanium-on-Insulator Formation by Thermal Mixing
SiGe FINFET WITH IMPROVED JUNCTION DOPING CONTROL
Techniques for Multiple Gate Workfunctions for a Nanowire CMOS Technology
Methods for Contact Formation for 10 Nanometers and Beyond with Minimal Mask Counts
Patent:
9,570,355 →
Application:
15/244,267 →
Method of Lateral Oxidation of Nfet and Pfet High-K Gate Stacks
Gate Planarity for Finfet Using Dummy Polish Stop
Forming Multi-Stack Nanowires Using a Common Release Material
Forming a Strained Semiconductor Layer Including Replacing an Etchable Material Formed Under the Strained Semiconductor Layer with a Dielectric Layer
Finfet Devices with Multiple Channel Lengths
Formation of Strained Fins in a Finfet Device
Finfet Devices with Multiple Channel Lengths
Overhang Hardmask to Prevent Parasitic Epitaxial Nodules at Gate End During Source Drain Epitaxy
Complementary Soi Lateral Bipolar Transistors with Backplate Bias
Silicon-Germanium Finfet Device with Controlled Junction
Dual Silicide Liner Flow for Enabling Low Contact Resistance
Preparation of Low Defect Density of Iii-V on Si for Device Fabrication
Methods for Contact Formation for 10 Nanometers and Beyond with Minimal Mask Counts
Uniform Height Tall Fins with Varying Silicon Germanium Concentrations
Decoupling Capacitor on Strain Relaxation Buffer Layer
Magnetic Trap for Cylindrical Diamagnetic Materials
III-V, SiGe, or Ge Base Lateral Bipolar Transistor and CMOS Hybrid Technology
Method and Structure to Fabricate Closely Packed Hybrid Nanowires at Scaled Pitch
Charge Carrier Transport Facilitated by Strain
Self-Aligned Punch Through Stopper Liner for Bulk Finfet
Electrostatically Enhanced Fins Field Effect Transistors
Tall Strained High Percentage Silicon Germanium Fins for Cmos
Method and Structure for Forming Finfet Cmos with Dual Doped Sti Regions
Field Effect Transistor Including Strained Germanium Fins
Porous Silicon Relaxation Medium for Dislocation Free Cmos Devices
Porous Silicon Relaxation Medium for Dislocation Free Cmos Devices
Adjacent Strained <100> Nfet Fins and <110> Pfet Fins
Hetero-Integration of Iii-N Material on Silicon
Enhanced Defect Reduction for Heteroepitaxy by Seed Shape Engineering
Method of Forming Field Effect Transistors (Fets) with Abrupt Junctions and Integrated Circuit Chips with the Fets
Uniform Dielectric Recess Depth During Fin Reveal
Method of Forming a Flexible Semiconductor Layer and Devices on a Flexible Carrier
Localized Elastic Strain Relaxed Buffer
Epitaxial Lift-Off Process with Guided Etching
Strain Relaxed Buffer Layers with Virtually Defect Free Regions
Cmos Compatible Fuse or Resistor Using Self-Aligned Contacts
Method and Structure to Fabricate Closely Packed Hybrid Nanowires at Scaled Pitch
Porous Fin as Compliant Medium to Form Dislocation-Free Heteroepitaxial Films
Porous Fin as Compliant Medium to Form Dislocation-Free Heteroepitaxial Films
Gate Planarity for Finfet Using Dummy Polish Stop
Method to Improve Finfet Cut Overlay
Method for Forming a Semiconductor Structure Containing High Mobility Semiconductor Channel Materials
Method for Forming a Semiconductor Structure Containing High Mobility Semiconductor Channel Materials
Hybrid ETSOI Structure to Minimize Noise Coupling from TSV
Uniform Dielectric Recess Depth During Fin Reveal
Uniform Dielectric Recess Depth During Fin Reveal
Double Aspect Ratio Trapping
Self-Forming Spacers Using Oxidation
Device Isolation for III-V Substrates
Extended Contact Area Using Undercut Silicide Extensions
Composite Manganese Nitride / Low-K Dielectric Cap
Cmos Compatible Fuse or Resistor Using Self-Aligned Contacts
Fabricating Semiconductor Devices by Cross-Linking and Removing Portions of Deposited Hsq
Patent:
10,170,308 →
Application:
15/730,239 →
Vertical Field Effect Transistor (Vfet) Programmable Complementary Metal Oxide Semiconductor Inverter
Method and Structure for Forming Finfet Cmos with Dual Doped Sti Regions
Porous Silicon Relaxation Medium for Dislocation Free Cmos Devices
Porous Silicon Relaxation Medium for Dislocation Free Cmos Devices
Simplified Block Patterning with Wet Strippable Hardmask for High-Energy Implantation
Surface Roughness of Iii-V Fin Formed on Silicon Sidewall by Implementing Sacrificial Buffers
Patent:
10,205,003 →
Application:
15/871,830 →
Method of Lateral Oxidation of Nfet and Pfet High-K Gate Stacks
Hybrid Iii-V Technology to Support Multiple Supply Voltages and Off State Currents on Same Chip
Method of Fabricating Electrostatically Enhanced Fins and Stacked Nanowire Field Effect Transistors
Charge Carrier Transport Facilitated by Strain
Germanium Dual-Fin Field Effect Transistor
Cmos Compatible Fuse or Resistor Using Self-Aligned Contacts
Self-Forming Spacers Using Oxidation
Finfet Devices with Multiple Channel Lengths
Magnetic Trap for Cylindrical Diamagnetic Materials
Device Isolation for III-V Substrates
Porous Silicon Relaxation Medium for Dislocation Free Cmos Devices
Vertical Field Effect Transistor (Vfet) Programmable Complementary Metal Oxide Semiconductor Inverter
Related Assignments
(12)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 12, 2001
From: CHU, JACK OON
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 012315/0877 →
Assignment of Assignor's Interest
Oct 17, 2003
From: ANDRY, PAUL S.; BUCHWALTER, LEENA P.; BUDD, RUSSELL A.; WASSICK, THOMAS A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 014618/0429 →
Assignment of Assignor's Interest
Apr 23, 2004
From: BEINTNER, JOCHEN C.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 014557/0523 →
Assignment of Assignor's Interest
Aug 3, 2004
From: COLBURN, MATTHEW E.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 014945/0577 →
Assignment of Assignor's Interest
Sep 20, 2004
From: FRANK, MARTIN M.; REZNICEK, ALEXANDER; GOUSEV, EVGENI P.; CARTIER, EDUARD A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 015151/0783 →
Assignment of Assignor's Interest
Mar 22, 2006
From: MILKOVE, KEITH RAYMOND; GAIDIS, MICHAEL CHRISTOPHER
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 017365/0024 →
Assignment of Assignor's Interest
Jan 17, 2007
From: CLEVENGER, LAWRENCE A.; COLBURN, MATTHEW E.; HSU, LOUIS C.; LI, WAI-KIN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 018783/0436 →
Assignment of Assignor's Interest
Jan 17, 2007
From: CLEVENGER, LAWRENCE A.; COLBURN, MATTHEW E.; HSU, LOUIS C.; LI, WAI-KIN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 018770/0151 →
Assignment of Assignor's Interest
Feb 6, 2007
From: CLEVENGER, LAWRENCE A.; COLBURN, MATTHEW E.; HSU, LOUIS C.; LI, WAI-KIN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 018859/0986 →
Assignment of Assignor's Interest
Dec 27, 2007
From: COHEN, GUY MOSHE
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020295/0054 →
Assignment of Assignor's Interest
Jan 13, 2010
From: OLYMPUS LIFE SCIENCE RESEARCH EUROPA GMBH
To: BECKMAN COULTER, INC.
Reel/Frame 023778/0153 →
Corrective Assignment to Correct the Receiving Party Address Previously Recorded on Reel 014618 Frame 0429. Assignor(S) Hereby Confirms the Assignment.
Jan 1, 2020
From: ANDRY, PAUL STEPHEN; BUCHWALTER, LEENA PAIVIKKI; BUDD, RUSSELL ALAN; WASSICK, THOMAS ANTHONY
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 051457/0679 →