Double aspect ratio trapping

1. A method of forming a semiconductor structure, said method comprising:

providing a semiconductor substrate comprising a first semiconductor material of a first lattice constant and containing a plurality of sacrificial trench isolation structures therein;

forming a plurality of first semiconductor-containing pillar structures comprising a second semiconductor material having a second lattice constant that is greater than said first lattice constant adjacent each sacrificial trench isolation structure and extending upwards from a first sub-surface of said semiconductor substrate;

forming a dielectric cap portion on a topmost surface of each first semiconductor-containing pillar structure, wherein a topmost surface of each dielectric cap portion is coplanar with a topmost surface of each sacrificial trench isolation structure of said plurality of sacrificial trench isolation structures;

removing each sacrificial trench isolation structure of said plurality of sacrificial trench isolation structures to expose a second sub-surface of said semiconductor substrate;

forming a dielectric spacer along sidewall surfaces of each first semiconductor-containing pillar structure and on a portion of said second sub-surface of said semiconductor substrate; and

forming a plurality of second semiconductor-containing pillar structures comprising a third semiconductor material having a third lattice constant that is greater than said first lattice constant adjacent said dielectric spacer and on another portion of said second sub-surface of said semiconductor substrate, wherein each of said second semiconductor-containing pillar structures has a width that is different from a width of each of said first semiconductor-containing pillar structures, and wherein said forming said plurality of second semiconductor-containing pillar structures comprises a semiconductor regrowth process and wherein said third semiconductor material includes a lower portion having a first defect density and an upper portion having a second defect density that is less than the first defect density.

2. The method of claim 1 , wherein said forming said semiconductor substrate containing said plurality of sacrificial trench isolation structures comprises:

forming a hard mask layer on a topmost surface of said semiconductor substrate;

patterning said hard mask layer and said semiconductor substrate to include a plurality of first trenches;

filling each first trench of said plurality of first trenches with a trench dielectric material; and

removing remaining portions of said hard mask layer from said topmost surface of said semiconductor substrate.

3. The method of claim 2 , wherein said patterning comprises a sidewall image transfer process.

4. The method of claim 1 , wherein said removing each sacrificial trench isolation structure of said plurality of sacrificial trench isolation structures comprises an anisotropic etching process.

5. The method of claim 1 , wherein said forming said dielectric cap portion on said topmost surface of each first semiconductor-containing pillar structure comprises:

recessing an upper portion of each first semiconductor-containing pillar structure;

depositing a dielectric cap material; and

planarizing said dielectric cap material.

6. The method of claim 5 , wherein a topmost surface of said dielectric cap portion is coplanar with a topmost surface of each second semiconductor-containing pillar structure and a topmost surface of each dielectric spacer.

7. The method of claim 1 , wherein each of said second semiconductor-containing pillar structures has a height that is greater than a height of each of said first semiconductor-containing pillar structures.

8. The method of claim 1 , wherein said second semiconductor material and said third semiconductor material comprise a same semiconductor material.

9. The method of claim 1 , wherein said second semiconductor material comprises a different semiconductor material than said third semiconductor material.

10. The method of claim 1 , wherein said first and second semiconductor pillar structures each comprises a lower portion having a first defect density and an upper portion having a second defect density that is less than the first defect density.

11. The method of claim 1 , wherein said first semiconductor material is silicon and said second and third semiconductor materials are selected from germanium, an III-V compound semiconductor and an II-VI compound semiconductor.

12. The method of claim 1 , wherein said second and third semiconductor materials have an epitaxial relationship with said semiconductor substrate portion.

13. The method of claim 1 , wherein a topmost surface of each second semiconductor-containing pillar structure is higher than a topmost surface of each first semiconductor-containing pillar structure.

14. The method of claim 13 , wherein a bottommost surface each second semiconductor-containing pillar structure is lower than a bottommost surface of each first semiconductor-containing pillar structure.

15. The method of claim 1 , wherein said first sub-surface of said semiconductor substrate portion that contains each first semiconductor-containing pillar structure is raised relative to said second sub-surface of said semiconductor portion that contains each second semiconductor-containing pillar structure.

16. A method of forming a semiconductor structure, said method comprising:

providing a semiconductor substrate comprising a first semiconductor material of a first lattice constant and containing a plurality of sacrificial trench isolation structures therein;

forming a plurality of first semiconductor-containing pillar structures comprising a second semiconductor material having a second lattice constant that is greater than said first lattice constant adjacent each sacrificial trench isolation structure and extending upwards from a first sub-surface of said semiconductor substrate;

forming a dielectric cap portion on a topmost surface of each first semiconductor-containing pillar structure, wherein a topmost surface of each dielectric cap portion is coplanar with a topmost surface of each sacrificial trench isolation structure of said plurality of sacrificial trench isolation structures;

removing each sacrificial trench isolation structure of said plurality of sacrificial trench isolation structures to expose a second sub-surface of said semiconductor substrate;

forming a dielectric spacer along sidewall surfaces of each first semiconductor-containing pillar structure and on a portion of said second sub-surface of said semiconductor substrate; and

forming a plurality of second semiconductor-containing pillar structures comprising a third semiconductor material having a third lattice constant that is greater than said first lattice constant adjacent said dielectric spacer and on another portion of said second sub-surface of said semiconductor substrate, wherein each of said second semiconductor-containing pillar structures has a width that is different from a width of each of said first semiconductor-containing pillar structures, and wherein said first and second semiconductor pillar structures each comprises a lower portion having a first defect density and an upper portion having a second defect density that is less than the first defect density.