Integrated circuit having strained fins on bulk substrate and method to fabricate same

1. A method, comprising:

forming a set of fins in a top portion of a semiconductor layer;

heating the set of fins to cause condensation of the fins, wherein a concentration of a first constituent semiconductor material of the set of fins is increased, and to also cause growth of an oxide from a second constituent semiconductor material of the set of fins at least on vertical side surfaces of the fins of the first set of fins;

masking a first sub-set of the set of fins and forming a plurality of voids in the oxide by removing a second sub-set of the set of fins, each void having a three-dimensional shape and dimensions that correspond to a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set of fins; and

epitaxially growing in the voids a third sub-set of fins, the third sub-set of fins being comprised of a semiconductor material that differs from at least one of the first constituent semiconductor material and the second constituent semiconductor material, where each fin of the third subset of fins has a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set of fins.

2. The method as in claim 1 , where the first set of fins is comprised of SiGe and where the third subset of fins comprised of Si.

3. The method as in claim 1 , where forming the set of fins comprises:

providing a substrate having on a top surface thereof the semiconductor layer as an overlying semiconductor layer, the overlying semiconductor layer comprised of a strain relaxed buffer comprised of a layer of Si 1-x Ge x , where x has a non-zero value=n;

defining a plurality of fins in a top portion of the layer of Si 1-x Ge x ; and

annealing the defined plurality of fins to form the set of fins as a set of condensed Si 1-x Ge x fins, where x has a value=m, where m>n.

4. The method as in claim 3 , where n is equal to about 0.25, and where in is equal to about 0.50.

5. The method as in claim 3 , where the substrate is comprised of a Si substrate having a graded layer of SiGe disposed between a top surface of the Si substrate and the strain relaxed buffer.

6. The method as in claim 3 , where individual ones of the fins of the plurality of fins have a first width, where the step of annealing consumes some of the Si 1-x Ge x of the fins to form the oxide, and where individual ones of the fins of the set of condensed Si 1-x Ge x fins have a second width that is less than the first width.

7. The method as in claim 3 , where the strain relaxed buffer is comprised of Si 1-x Ge x , where x has the non-zero value=n, where the step of annealing also condenses a top surface portion of the strain relaxed buffer to form a layer of condensed Si 1-x Ge x disposed between individual ones of the set of fins, where x has the value=m, where the step of annealing also forms a layer of oxide over the layer of condensed Si 1-x Ge x and between individual ones of the set of fins, and where the voids are also at least partially formed in the layer of oxide.

8. The method as in claim 7 , further comprising:

removing the oxide on the vertical side surfaces of the fins and the layer of oxide;

depositing a further layer of oxide on the layer of condensed Si 1-x Ge x between individual ones of the first and the third sub-set of fins; and

adjusting a thickness of the further layer of oxide so as to define a final height of each of the first and third sub-sets of fins relative to a top surface of the further layer of oxide.

9. The method as in claim 8 , where the step of depositing the further layer of oxide comprises an initial step of counter-doping a bottom portion of the first and the third sub-sets of fins to provide electrical isolation.

10. The method as in claim 1 , where individual ones of the set of fins comprise a hard mask disposed on a top of each individual ones of the set of fins.

11. A method, comprising:

providing a substrate having on a top surface thereof an overlying semiconductor layer, the overlying semiconductor layer comprised of a strain relaxed buffer comprised of a layer of Si 1-x Ge x , where x has a non-zero value=n;

defining a plurality of fins in a top portion of the layer of Si 1-x Ge x ;

annealing the defined plurality of fins to form a set of condensed Si 1-x Ge x fins, where x has a value=m, where m>n, where the step of annealing forms an oxide that covers at least vertical surfaces of individual ones of the set of condensed Si 1-x Ge x fins;

masking a first sub-set of the set of condensed Si 1-x Ge x fins;

forming a plurality of voids in the oxide by a step of removing a second sub-set of the set of condensed Si 1-x Ge x fins, each void having a three-dimensional shape and dimensions that correspond to a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set of the set of condensed Si 1-x Ge x fins; and

epitaxially growing strained Si in the voids to form a third sub-set of fins, where each fin of the third subset of fins has a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set of fins.

12. The method as in claim 11 , where n is equal to about 0.25, and where m is equal to about 0.50.

13. The method as in claim 11 , where the substrate is comprised of a Si substrate having a graded layer of SiGe disposed between a top surface of the Si substrate and the strain relaxed buffer.

14. The method as in claim 11 , where individual ones of the fins of the plurality of fins have a first width, where the step of annealing consumes some of the Si 1-x Ge x of the fins to form the oxide, and where individual ones of the fins of the set of condensed Si 1-x Ge x fins have a second width that is less than the first width.

15. The method as in claim 11 , where the step of annealing also condenses a top surface portion of the strain relaxed buffer to form a layer of condensed Si 1-x Ge x disposed between individual ones of the set of condensed Si 1-x Ge x fins, where x has the value=m, where the step of annealing also forms a layer of oxide over the layer of condensed Si 1-x Ge x and between individual ones of the set of condensed Si 1-x Ge x fins, and where the voids are also at least partially formed in the layer of oxide.

16. The method as in claim 15 , further comprising:

removing the oxide on the vertical side surfaces of the fins and the layer of oxide;

depositing a further layer of oxide on the layer of condensed Si 1-x Ge x between individual ones of the first and the third sub-set of fins; and

adjusting a thickness of the further layer of oxide so as to define a final height of each of the first and third sub-sets of fins relative to a top surface of the further layer of oxide.

17. The method as in claim 16 , where the step of depositing the further layer of oxide comprises an initial step of counter-doping a bottom portion of the first and the third sub-sets of fins to provide electrical isolation.

18. A method, comprising:

forming a set of fins in a top portion of a strain relaxed buffer layer comprised of SiGe, wherein individual ones of the fins of the set of fins are comprised of SiGe;

annealing the set of fins to cause condensation of the fins and growth of an oxide at least on vertical side surfaces thereof, where annealing consumes a portion of the Si of the SiGe to grow the oxide as a layer of SiO 2 on the vertical side surfaces of the set of fins and also increases a Ge concentration in a remaining portion of the SiGe in the set of fins;

masking a first sub-set of the set of fins and forming a plurality of voids in the oxide by removing a second sub-set of the set of fins, each void having a three-dimensional shape and dimensions that correspond to a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set of fins; and

epitaxially growing in the voids a third sub-set of fins, the third sub-set of fins being comprised of semiconductor material, where each fin of the third subset of fins has a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set of fins;

where the step of annealing also consumes a portion of the Si in a top surface portion of the strain relaxed buffer layer between individual ones of the fins to grow a surface layer of SiO 2 on the top of the strain relaxed buffer layer and also increases a Ge concentration in the top surface portion of the strain relaxed buffer layer.

19. The method as in claim 18 , further comprising:

removing the SiO 2 on the vertical side surfaces of the fins and also the surface layer of SiO 2 ; and

forming a layer of oxide on the top of the strain relaxed buffer layer between individual ones of the fins of the first sub-set of fins and the third sub-set of fins; where

a final height of each of the furs of the first sub-set of fins and the third sub-set of fins is relative to a top surface of the formed layer of oxide.

20. The method as in claim 19 , where the step of forming the layer of oxide comprises an initial step of counter-doping a bottom portion of each of the fins of the first sub-set of fins and the third sub-set of fins to provide electrical isolation.