Complementary SOI lateral bipolar transistors with backplate bias

1. A method for fabricating a complementary bipolar junction transistor (BJT) integrated structure, the method comprising:

forming a first backplate in a monolithic substrate below a first buried oxide (BOX) layer;

forming a second backplate in the monolithic substrate below the first BOX layer, the second backplate being electrically isolated from the first backplate;

forming an NPN lateral BJT above the first BOX layer and superposing the first backplate, the NPN lateral BJT configured to conduct electricity horizontally between an NPN emitter and an NPN collector when the NPN lateral BJT is active;

forming a PNP lateral BJT superposing the second backplate, the PNP lateral BJT configured to conduct electricity horizontally between a PNP emitter and a PNP collector when the PNP lateral BJT is active;

wherein forming the first backplate includes forming the first backplate above a second BOX layer such that the first backplate is electrically isolated from the monolithic substrate; and

wherein forming the second backplate includes forming the second backplate above the second BOX layer such that the second backplate is electrically isolated from the monolithic substrate.

2. The method of claim 1 , further comprising forming shallow trench isolation (STI) between a first region for forming the NPN lateral BJT and a second region for forming the PNP lateral BJT.

3. The method of claim 1 , further comprising:

doping the first backplate with n+ dopant; and

doping the second backplate with p+ dopant.

4. The method of claim 1 , wherein the NPN lateral BJT and the PNP lateral BJT are heterojunction BJTs.

5. The method of claim 1 , further comprising:

electrically coupling an NPN base of the NPN lateral BJT to a PNP base of the PNP lateral BJT; and

electrically coupling the NPN collector of the NPN lateral BJT to the PNP collector of the PNP lateral BJT.

6. The method of claim 1 , further comprising:

etching a first backplate trench through the first BOX layer to the first backplate; and

growing n+ silicon over the first backplate in the first backplate via and through the first BOX layer.

7. The method of claim 1 , further comprising:

etching a second backplate via through the first BOX layer to the second backplate; and

growing p+ silicon over the second backplate in the second backplate via and through the first BOX layer.

8. The method of claim 1 , further comprising:

implanting the NPN collector and the NPN emitter with n+ material; and

implanting the PNP collector and the PNP emitter with p+ material.