IP Library Granted Patent US 10,170,308
Granted Patent B1
US 10,170,308 · App. 15/730,239 · Granted Jan 1, 2019

Fabricating semiconductor devices by cross-linking and removing portions of deposited HSQ

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,170,308
App. No.
15/730,239
Granted
Jan 1, 2019
Kind
B1
Abstract

A method of manufacturing a semiconductor device comprises forming a hydrogen silesquioxane (HSQ) layer on a semiconductor substrate, forming a cap layer on the HSQ layer, cross-linking a portion of the HSQ layer under the cap layer, and removing another portion of the HSQ layer which was not cross-linked.

Claims (30)

1. A method of manufacturing a semiconductor device, comprising:

forming a hydrogen silesquioxane (HSQ) layer on a semiconductor substrate;

forming a cap layer on the HSQ layer;

cross-linking a portion of the HSQ layer under the cap layer;

removing another portion of the HSQ layer which was not cross-linked;

forming a dielectric layer on the substrate, wherein the dielectric layer is positioned between the HSQ layer and the semiconductor substrate;

forming at least one opening exposing a portion of the semiconductor substrate through the cap layer, HSQ layer and dielectric layer; and

epitaxially growing a III-V semiconductor material from the exposed portion of the semiconductor substrate, wherein the III-V semiconductor material occupies a vacant area left by the removal of the other portion of the HSQ layer was not cross-linked;

wherein the removing comprises introducing a developer through the at least one opening to remove the other portion of the HSQ layer which was not cross-linked.

2. The method according to claim 1 , wherein the cross-linking is performed using one of optical lithography and electron beam (e-beam) lithography.

3. The method according to claim 1 , wherein the cap layer comprises at least one of aluminum oxide, a low-temperature oxide, a low-temperature nitride, spin-on glass (SOG) and silicon anti-reflective coating (SiARC).

4. The method according to claim 1 , wherein the cap layer is deposited on the HSQ layer at a temperature which is less than a threshold temperature for cross-linking the HSQ layer.

5. The method according to claim 1 , wherein:

the vacant area is bordered by the cross-linked portion of the HSQ layer under the cap layer.

6. The method according to claim 1 , further comprising forming another HSQ layer on the cap layer.

7. The method according to claim 6 , wherein the cross-linking comprises performing an exposure process, wherein a portion of the other HSQ layer on the cap layer is cross-linked during the exposure process with the portion of the HSQ layer under the cap layer.

8. The method according to claim 7 , wherein the portion of the other HSQ layer on the cap layer is aligned with the portion of the HSQ layer under the cap layer.

9. A method of manufacturing a semiconductor device, comprising:

forming a hydrogen silesquioxane (HSQ) layer on a semiconductor substrate;

forming a cap layer on the HSQ layer;

cross-linking a portion of the HSQ layer under the cap layer;

removing another portion of the HSQ layer which was not cross-linked;

forming a dielectric layer on the substrate, wherein the dielectric layer is positioned between the HSQ layer and the semiconductor substrate;

forming at least one opening exposing a portion of the semiconductor substrate through the cap layer, HSQ layer and dielectric layer;

wherein:

the removing comprises introducing a developer through the at least one opening to remove the other portion of the HSQ layer which was not cross-linked;

a vacant area is left by the removal of the other portion of the HSQ layer layer which was not cross-linked;

the vacant area is bordered by the cross-linked portion of the HSQ layer under the cap layer;

the vacant area is further bordered by the cap layer on a top portion of the vacant area; and

epitaxially growing a III-V semiconductor material from the exposed portion of the substrate in the vacant area.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052620/0961 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2017
From: COHEN, GUY; HASHEMI, POUYA; LEE, SANGHOON; REZNICEK, ALEXANDER
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 043840/0401 →