IP Library Granted Patent US 9,601,386
Granted Patent B1
US 9,601,386 · App. 14/851,838 · Granted Mar 21, 2017

Fin isolation on a bulk wafer

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,601,386
App. No.
14/851,838
Granted
Mar 21, 2017
Kind
B1
Abstract

A method for forming a semiconductor device includes etching first fins into a bulk semiconductor substrate and exposing a portion of the first fins through a first dielectric layer formed over the first fins. A first film is deposited over the first fins in a region for n-type devices. and a second film is deposited over the first fins in a region for p-type devices. The first film and the second film are etched to form second fins in the regions for n-type devices and for the region for p-type devices. The second fins are protected. The first fins are removed from the first dielectric layer to form an isolation layer separating the second fins from the substrate.

Claims (49)

1. A method for forming a semiconductor device, comprising:

etching first fins into a bulk semiconductor substrate;

exposing a portion of the first fins through a first dielectric layer formed over the first fins;

depositing a first film over the first fins in a region for n-type devices;

depositing a second film over the first fins in a region for p-type devices;

etching the first film and the second film to form second fins in the regions for n-type devices and for the region for p-type devices;

protecting the second fins; and

removing the first fins from the first dielectric layer to form an isolation layer separating the second fins from the substrate.

2. The method as recited in claim 1 , wherein depositing the first film over the first fins in a region for n-type devices includes epitaxially growing the first film on the first fins.

3. The method as recited in claim 1 , wherein depositing the second film over the first fins in a region for p-type devices includes:

epitaxially growing materials for the second film on the first fins; and

thermally mixing the materials to form the second film.

4. The method as recited in claim 1 , wherein at least one of the first film and the second film includes an amorphous phase and further comprising: recrystallizing the at least one of the first film and the second film.

5. The method as recited in claim 1 , wherein etching the first film and the second film includes patterning the first film and the second film such that the second fins are formed over dielectric material of the first dielectric layer.

6. The method as recited in claim 5 , wherein the first fins and the second fins are staggered to prevent vertical alignment.

7. The method as recited in claim 1 , wherein protecting the second fins includes encapsulating the second fins in a sacrificial dielectric material.

8. The method as recited in claim 1 , wherein removing includes:

etching the first fins; and

depositing a dielectric material in trenches left by removing the first fins.

9. The method as recited in claim 1 , wherein removing includes oxidizing the first fins.

10. A method for forming a semiconductor device, comprising:

etching first fins into a bulk semiconductor substrate, the first fins including Si;

exposing a portion of the first fins through a first dielectric layer formed over the first fins;

depositing and thermally mixing a SiGe film over the first fins in a region for p-type devices;

depositing a Si film over the first fins in a region for n-type devices after the thermal mixing to prevent Ge diffusion into the Si film;

etching the Si film and the SiGe film to form second fins in the regions for n-type devices and p-type devices;

protecting the second fins; and

removing the first fins from the first dielectric layer to form an isolation layer separating the second fins from the substrate.

11. The method as recited in claim 10 , wherein depositing the Si film over the first fins in a region for n-type devices includes epitaxially growing the Si film on the first fins using the first fins as a seed layer.

12. The method as recited in claim 10 , wherein depositing the SiGe film over the first fins in a region for p-type devices includes epitaxially growing SiGe materials for the SiGe film on the first fins.

13. The method as recited in claim 10 , wherein at least one of the Si film and the SiGe film includes an amorphous phase and further comprising: recrystallizing the at least one of the Si film and the SiGe film.

14. The method as recited in claim 10 , wherein etching the Si film and the SiGe film includes patterning the Si film and the SiGe film such that the second fins are formed over dielectric material of the first dielectric layer.

15. The method as recited in claim 14 , wherein the first fins and the second fins are staggered to prevent vertical alignment.

16. The method as recited in claim 10 , wherein protecting the second fins include encapsulating the second fins in a sacrificial dielectric material.

17. The method as recited in claim 10 , wherein removing includes:

etching the first fins; and

depositing a dielectric material in trenches left by removing the first fins.

18. A method for forming a semiconductor device, comprising:

etching first fins into a bulk semiconductor substrate, the first fins including Si;

exposing a portion of the first fins through a first dielectric layer formed over the first fins;

depositing and thermally mixing a SiGe film over the first fins in a region for p-type devices;

depositing a Si film over the first fins in a region for n-type devices after the thermal mixing to prevent Ge diffusion into the Si film;

planarizing the Si and SiGe films;

patterning the Si film and the SiGe film to form second fins in the regions for n-type and p-type devices wherein the second fins are formed over dielectric material of the first dielectric layer and are staggered from the first fins to prevent vertical alignment;

protecting the second fins using a hardmask and spacers to encapsulate the second fins;

removing the first fins from the first dielectric layer; and

restoring material in the first dielectric layer to form an isolation layer separating the second fins from the substrate.

19. The method as recited in claim 18 , wherein at least one of the Si film and the SiGe film includes an amorphous phase and further comprising: recrystallizing the at least one of the Si film and the SiGe film.

20. The method as recited in claim 18 , wherein restoring material in the first dielectric layer includes depositing a dielectric material in trenches left by removing the first fins.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052620/0961 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2015
From: HE, HONG; LI, JUNTAO; WANG, JUNLI; YANG, CHIH-CHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 036545/0336 →