Methods for contact formation for 10 nanometers and beyond with minimal mask counts
View Patent ↗A method of making a semiconductor device includes depositing a hard mask on a dielectric layer on a substrate, the dielectric layer being disposed around first, second, and third gates; removing a portion of the hard mask to form an opening that exposes the first, second, and third gates; forming a patterned soft mask on the first, second, and third gates within the opening, a first portion of the patterned soft mask being disposed on the first and second gates, and a second portion of the patterned soft mask being disposed on the second and third gates; removing portions of the dielectric layer to transfer the pattern of the patterned soft mask into the dielectric layer and form first and second contact openings between the first and second gates, and third and fourth contact openings between the second and third gates; and disposing a conductive material in the contact openings.
1. A semiconductor device, comprising:
a first gate and a second gate disposed on a substrate, a dielectric material layer disposed on the substrate around and between the first gate and the second gate;
a patterned hard mask arranged on the dielectric material layer, the patterned hard mask having an opening that exposes surfaces of the first gate and the second gate; and
a patterned soft mask arranged on the dielectric material layer between the first gate and the second gate such that a portion of a hard mask arranged on the first gate is exposed, and a portion of a hard mask arranged on the second gate is exposed;
wherein the dielectric material layer between the first gate and the second gate extends from a sidewall of the first gate to a sidewall of the second gate, has a sidewall that is substantially perpendicular to the first gate and the second gate, and a top surface of the dielectric material layer is substantially flush with a top surface of the hard mask of the first gate and a top surface of the hard mask of the second gate.
2. The semiconductor device of claim 1 , wherein the hard mask of the first gate and the hard mask of the second gate is silicon nitride.
3. The semiconductor device of claim 1 , wherein the patterned hard mask is amorphous silicon, titanium nitride, or a combination thereof.
4. The semiconductor device of claim 1 , wherein the patterned soft mask is photoresist material, a polymeric material, or a combination thereof.
5. The semiconductor device of claim 1 , wherein the dielectric material layer is only arranged beneath the patterned soft mask between the first gate and the second gate.
6. The semiconductor device of claim 5 , wherein two contact openings extend between the first gate and the second gate, the two contact openings being separated by the dielectric material layer.